derek.holloway
7502bf64a4
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77 lines
3.2 KiB
LLVM
77 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
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; RUN: -mcpu=pwr8 | FileCheck %s --check-prefix=POWER-8
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
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; RUN: -mcpu=pwr8 -mattr=-altivec | FileCheck %s --check-prefix=POWER-8-NO-ALTIVEC
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
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; RUN: -mcpu=pwr9 | FileCheck %s --check-prefix=POWER-9
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \
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; RUN: -mcpu=pwr9 -vec-extabi | FileCheck %s --check-prefix=POWER-9
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
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; RUN: -mcpu=pwr9 -mattr=-altivec | FileCheck %s --check-prefix=POWER-9-NO-ALTIVEC
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \
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; RUN: -mcpu=pwr9 -mattr=-altivec | FileCheck %s --check-prefix=POWER-9-NO-ALTIVEC
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declare i64 @llvm.bswap.i64(i64)
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; This patch verifies that the compiler generates optimized assembly for Power 8 64-bit
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; byte swap operations that enables instruction-level parallelism.
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define i64 @bswap64(i64 %x) {
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; POWER-8-LABEL: bswap64:
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; POWER-8: # %bb.0: # %entry
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; POWER-8-NEXT: rotlwi 4, 3, 8
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; POWER-8-NEXT: rldicl 5, 3, 32, 32
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; POWER-8-NEXT: rlwimi 4, 3, 24, 0, 7
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; POWER-8-NEXT: rlwimi 4, 3, 24, 16, 23
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; POWER-8-NEXT: rotlwi 3, 5, 8
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; POWER-8-NEXT: rlwimi 3, 5, 24, 0, 7
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; POWER-8-NEXT: rlwimi 3, 5, 24, 16, 23
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; POWER-8-NEXT: rldimi 3, 4, 32, 0
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; POWER-8-NEXT: blr
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;
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; POWER-8-NO-ALTIVEC-LABEL: bswap64:
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; POWER-8-NO-ALTIVEC: # %bb.0: # %entry
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; POWER-8-NO-ALTIVEC-NEXT: rotldi 5, 3, 16
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; POWER-8-NO-ALTIVEC-NEXT: rotldi 4, 3, 8
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; POWER-8-NO-ALTIVEC-NEXT: rldimi 4, 5, 8, 48
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; POWER-8-NO-ALTIVEC-NEXT: rotldi 5, 3, 24
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; POWER-8-NO-ALTIVEC-NEXT: rldimi 4, 5, 16, 40
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; POWER-8-NO-ALTIVEC-NEXT: rotldi 5, 3, 32
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; POWER-8-NO-ALTIVEC-NEXT: rldimi 4, 5, 24, 32
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; POWER-8-NO-ALTIVEC-NEXT: rotldi 5, 3, 48
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; POWER-8-NO-ALTIVEC-NEXT: rldimi 4, 5, 40, 16
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; POWER-8-NO-ALTIVEC-NEXT: rotldi 5, 3, 56
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; POWER-8-NO-ALTIVEC-NEXT: rldimi 4, 5, 48, 8
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; POWER-8-NO-ALTIVEC-NEXT: rldimi 4, 3, 56, 0
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; POWER-8-NO-ALTIVEC-NEXT: mr 3, 4
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; POWER-8-NO-ALTIVEC-NEXT: blr
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;
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; POWER-9-LABEL: bswap64:
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; POWER-9: # %bb.0: # %entry
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; POWER-9-NEXT: mtvsrdd 34, 3, 3
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; POWER-9-NEXT: xxbrd 0, 34
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; POWER-9-NEXT: mffprd 3, 0
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; POWER-9-NEXT: blr
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;
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; POWER-9-NO-ALTIVEC-LABEL: bswap64:
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; POWER-9-NO-ALTIVEC: # %bb.0: # %entry
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; POWER-9-NO-ALTIVEC-NEXT: rotldi 5, 3, 16
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; POWER-9-NO-ALTIVEC-NEXT: rotldi 4, 3, 8
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; POWER-9-NO-ALTIVEC-NEXT: rldimi 4, 5, 8, 48
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; POWER-9-NO-ALTIVEC-NEXT: rotldi 5, 3, 24
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; POWER-9-NO-ALTIVEC-NEXT: rldimi 4, 5, 16, 40
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; POWER-9-NO-ALTIVEC-NEXT: rotldi 5, 3, 32
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; POWER-9-NO-ALTIVEC-NEXT: rldimi 4, 5, 24, 32
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; POWER-9-NO-ALTIVEC-NEXT: rotldi 5, 3, 48
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; POWER-9-NO-ALTIVEC-NEXT: rldimi 4, 5, 40, 16
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; POWER-9-NO-ALTIVEC-NEXT: rotldi 5, 3, 56
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; POWER-9-NO-ALTIVEC-NEXT: rldimi 4, 5, 48, 8
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; POWER-9-NO-ALTIVEC-NEXT: rldimi 4, 3, 56, 0
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; POWER-9-NO-ALTIVEC-NEXT: mr 3, 4
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; POWER-9-NO-ALTIVEC-NEXT: blr
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entry:
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%0 = call i64 @llvm.bswap.i64(i64 %x)
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ret i64 %0
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}
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