derek.holloway
7502bf64a4
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470 lines
14 KiB
LLVM
470 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
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; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINX %s
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; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
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; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
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; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFHMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
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; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFHMIN %s
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; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs < %s \
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; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINXMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs < %s \
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; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINXMIN %s
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define half @select_icmp_eq(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_eq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: beq a0, a1, .LBB0_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: ret
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;
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; CHECKIZHINX-LABEL: select_icmp_eq:
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; CHECKIZHINX: # %bb.0:
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; CHECKIZHINX-NEXT: beq a0, a1, .LBB0_2
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; CHECKIZHINX-NEXT: # %bb.1:
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; CHECKIZHINX-NEXT: mv a2, a3
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; CHECKIZHINX-NEXT: .LBB0_2:
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; CHECKIZHINX-NEXT: mv a0, a2
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; CHECKIZHINX-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: select_icmp_eq:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: beq a0, a1, .LBB0_2
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; CHECKIZFHMIN-NEXT: # %bb.1:
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; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
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; CHECKIZFHMIN-NEXT: .LBB0_2:
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; CHECKIZFHMIN-NEXT: ret
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;
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; CHECKIZHINXMIN-LABEL: select_icmp_eq:
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; CHECKIZHINXMIN: # %bb.0:
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; CHECKIZHINXMIN-NEXT: beq a0, a1, .LBB0_2
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; CHECKIZHINXMIN-NEXT: # %bb.1:
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; CHECKIZHINXMIN-NEXT: mv a2, a3
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; CHECKIZHINXMIN-NEXT: .LBB0_2:
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; CHECKIZHINXMIN-NEXT: mv a0, a2
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; CHECKIZHINXMIN-NEXT: ret
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%1 = icmp eq i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_ne(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_ne:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bne a0, a1, .LBB1_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: ret
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;
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; CHECKIZHINX-LABEL: select_icmp_ne:
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; CHECKIZHINX: # %bb.0:
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; CHECKIZHINX-NEXT: bne a0, a1, .LBB1_2
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; CHECKIZHINX-NEXT: # %bb.1:
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; CHECKIZHINX-NEXT: mv a2, a3
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; CHECKIZHINX-NEXT: .LBB1_2:
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; CHECKIZHINX-NEXT: mv a0, a2
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; CHECKIZHINX-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: select_icmp_ne:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: bne a0, a1, .LBB1_2
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; CHECKIZFHMIN-NEXT: # %bb.1:
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; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
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; CHECKIZFHMIN-NEXT: .LBB1_2:
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; CHECKIZFHMIN-NEXT: ret
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;
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; CHECKIZHINXMIN-LABEL: select_icmp_ne:
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; CHECKIZHINXMIN: # %bb.0:
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; CHECKIZHINXMIN-NEXT: bne a0, a1, .LBB1_2
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; CHECKIZHINXMIN-NEXT: # %bb.1:
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; CHECKIZHINXMIN-NEXT: mv a2, a3
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; CHECKIZHINXMIN-NEXT: .LBB1_2:
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; CHECKIZHINXMIN-NEXT: mv a0, a2
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; CHECKIZHINXMIN-NEXT: ret
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%1 = icmp ne i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_ugt(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_ugt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bltu a1, a0, .LBB2_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB2_2:
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; CHECK-NEXT: ret
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;
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; CHECKIZHINX-LABEL: select_icmp_ugt:
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; CHECKIZHINX: # %bb.0:
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; CHECKIZHINX-NEXT: bltu a1, a0, .LBB2_2
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; CHECKIZHINX-NEXT: # %bb.1:
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; CHECKIZHINX-NEXT: mv a2, a3
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; CHECKIZHINX-NEXT: .LBB2_2:
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; CHECKIZHINX-NEXT: mv a0, a2
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; CHECKIZHINX-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: select_icmp_ugt:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: bltu a1, a0, .LBB2_2
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; CHECKIZFHMIN-NEXT: # %bb.1:
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; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
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; CHECKIZFHMIN-NEXT: .LBB2_2:
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; CHECKIZFHMIN-NEXT: ret
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;
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; CHECKIZHINXMIN-LABEL: select_icmp_ugt:
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; CHECKIZHINXMIN: # %bb.0:
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; CHECKIZHINXMIN-NEXT: bltu a1, a0, .LBB2_2
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; CHECKIZHINXMIN-NEXT: # %bb.1:
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; CHECKIZHINXMIN-NEXT: mv a2, a3
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; CHECKIZHINXMIN-NEXT: .LBB2_2:
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; CHECKIZHINXMIN-NEXT: mv a0, a2
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; CHECKIZHINXMIN-NEXT: ret
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%1 = icmp ugt i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_uge(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_uge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bgeu a0, a1, .LBB3_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB3_2:
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; CHECK-NEXT: ret
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;
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; CHECKIZHINX-LABEL: select_icmp_uge:
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; CHECKIZHINX: # %bb.0:
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; CHECKIZHINX-NEXT: bgeu a0, a1, .LBB3_2
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; CHECKIZHINX-NEXT: # %bb.1:
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; CHECKIZHINX-NEXT: mv a2, a3
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; CHECKIZHINX-NEXT: .LBB3_2:
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; CHECKIZHINX-NEXT: mv a0, a2
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; CHECKIZHINX-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: select_icmp_uge:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: bgeu a0, a1, .LBB3_2
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; CHECKIZFHMIN-NEXT: # %bb.1:
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; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
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; CHECKIZFHMIN-NEXT: .LBB3_2:
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; CHECKIZFHMIN-NEXT: ret
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;
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; CHECKIZHINXMIN-LABEL: select_icmp_uge:
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; CHECKIZHINXMIN: # %bb.0:
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; CHECKIZHINXMIN-NEXT: bgeu a0, a1, .LBB3_2
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; CHECKIZHINXMIN-NEXT: # %bb.1:
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; CHECKIZHINXMIN-NEXT: mv a2, a3
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; CHECKIZHINXMIN-NEXT: .LBB3_2:
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; CHECKIZHINXMIN-NEXT: mv a0, a2
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; CHECKIZHINXMIN-NEXT: ret
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%1 = icmp uge i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_ult(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_ult:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bltu a0, a1, .LBB4_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: ret
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;
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; CHECKIZHINX-LABEL: select_icmp_ult:
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; CHECKIZHINX: # %bb.0:
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; CHECKIZHINX-NEXT: bltu a0, a1, .LBB4_2
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; CHECKIZHINX-NEXT: # %bb.1:
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; CHECKIZHINX-NEXT: mv a2, a3
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; CHECKIZHINX-NEXT: .LBB4_2:
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; CHECKIZHINX-NEXT: mv a0, a2
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; CHECKIZHINX-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: select_icmp_ult:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: bltu a0, a1, .LBB4_2
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; CHECKIZFHMIN-NEXT: # %bb.1:
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; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
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; CHECKIZFHMIN-NEXT: .LBB4_2:
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; CHECKIZFHMIN-NEXT: ret
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;
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; CHECKIZHINXMIN-LABEL: select_icmp_ult:
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; CHECKIZHINXMIN: # %bb.0:
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; CHECKIZHINXMIN-NEXT: bltu a0, a1, .LBB4_2
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; CHECKIZHINXMIN-NEXT: # %bb.1:
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; CHECKIZHINXMIN-NEXT: mv a2, a3
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; CHECKIZHINXMIN-NEXT: .LBB4_2:
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; CHECKIZHINXMIN-NEXT: mv a0, a2
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; CHECKIZHINXMIN-NEXT: ret
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%1 = icmp ult i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_ule(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_ule:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bgeu a1, a0, .LBB5_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB5_2:
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; CHECK-NEXT: ret
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;
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; CHECKIZHINX-LABEL: select_icmp_ule:
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; CHECKIZHINX: # %bb.0:
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; CHECKIZHINX-NEXT: bgeu a1, a0, .LBB5_2
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; CHECKIZHINX-NEXT: # %bb.1:
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; CHECKIZHINX-NEXT: mv a2, a3
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; CHECKIZHINX-NEXT: .LBB5_2:
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; CHECKIZHINX-NEXT: mv a0, a2
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; CHECKIZHINX-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: select_icmp_ule:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: bgeu a1, a0, .LBB5_2
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; CHECKIZFHMIN-NEXT: # %bb.1:
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; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
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; CHECKIZFHMIN-NEXT: .LBB5_2:
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; CHECKIZFHMIN-NEXT: ret
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;
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; CHECKIZHINXMIN-LABEL: select_icmp_ule:
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; CHECKIZHINXMIN: # %bb.0:
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; CHECKIZHINXMIN-NEXT: bgeu a1, a0, .LBB5_2
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; CHECKIZHINXMIN-NEXT: # %bb.1:
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; CHECKIZHINXMIN-NEXT: mv a2, a3
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; CHECKIZHINXMIN-NEXT: .LBB5_2:
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; CHECKIZHINXMIN-NEXT: mv a0, a2
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; CHECKIZHINXMIN-NEXT: ret
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%1 = icmp ule i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_sgt(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_sgt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: blt a1, a0, .LBB6_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB6_2:
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; CHECK-NEXT: ret
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;
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; CHECKIZHINX-LABEL: select_icmp_sgt:
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; CHECKIZHINX: # %bb.0:
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; CHECKIZHINX-NEXT: blt a1, a0, .LBB6_2
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; CHECKIZHINX-NEXT: # %bb.1:
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; CHECKIZHINX-NEXT: mv a2, a3
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; CHECKIZHINX-NEXT: .LBB6_2:
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; CHECKIZHINX-NEXT: mv a0, a2
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; CHECKIZHINX-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: select_icmp_sgt:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: blt a1, a0, .LBB6_2
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; CHECKIZFHMIN-NEXT: # %bb.1:
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; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
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; CHECKIZFHMIN-NEXT: .LBB6_2:
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; CHECKIZFHMIN-NEXT: ret
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;
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; CHECKIZHINXMIN-LABEL: select_icmp_sgt:
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; CHECKIZHINXMIN: # %bb.0:
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; CHECKIZHINXMIN-NEXT: blt a1, a0, .LBB6_2
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; CHECKIZHINXMIN-NEXT: # %bb.1:
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; CHECKIZHINXMIN-NEXT: mv a2, a3
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; CHECKIZHINXMIN-NEXT: .LBB6_2:
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; CHECKIZHINXMIN-NEXT: mv a0, a2
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; CHECKIZHINXMIN-NEXT: ret
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%1 = icmp sgt i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_sge(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_sge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bge a0, a1, .LBB7_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fmv.h fa0, fa1
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; CHECK-NEXT: .LBB7_2:
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; CHECK-NEXT: ret
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;
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; CHECKIZHINX-LABEL: select_icmp_sge:
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; CHECKIZHINX: # %bb.0:
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; CHECKIZHINX-NEXT: bge a0, a1, .LBB7_2
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; CHECKIZHINX-NEXT: # %bb.1:
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; CHECKIZHINX-NEXT: mv a2, a3
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; CHECKIZHINX-NEXT: .LBB7_2:
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; CHECKIZHINX-NEXT: mv a0, a2
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; CHECKIZHINX-NEXT: ret
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;
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; CHECKIZFHMIN-LABEL: select_icmp_sge:
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; CHECKIZFHMIN: # %bb.0:
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; CHECKIZFHMIN-NEXT: bge a0, a1, .LBB7_2
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; CHECKIZFHMIN-NEXT: # %bb.1:
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; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
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; CHECKIZFHMIN-NEXT: .LBB7_2:
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; CHECKIZFHMIN-NEXT: ret
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;
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; CHECKIZHINXMIN-LABEL: select_icmp_sge:
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; CHECKIZHINXMIN: # %bb.0:
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; CHECKIZHINXMIN-NEXT: bge a0, a1, .LBB7_2
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; CHECKIZHINXMIN-NEXT: # %bb.1:
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; CHECKIZHINXMIN-NEXT: mv a2, a3
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; CHECKIZHINXMIN-NEXT: .LBB7_2:
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; CHECKIZHINXMIN-NEXT: mv a0, a2
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; CHECKIZHINXMIN-NEXT: ret
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%1 = icmp sge i32 %a, %b
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%2 = select i1 %1, half %c, half %d
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ret half %2
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}
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define half @select_icmp_slt(i32 signext %a, i32 signext %b, half %c, half %d) {
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; CHECK-LABEL: select_icmp_slt:
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; CHECK: # %bb.0:
|
|
; CHECK-NEXT: blt a0, a1, .LBB8_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: fmv.h fa0, fa1
|
|
; CHECK-NEXT: .LBB8_2:
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECKIZHINX-LABEL: select_icmp_slt:
|
|
; CHECKIZHINX: # %bb.0:
|
|
; CHECKIZHINX-NEXT: blt a0, a1, .LBB8_2
|
|
; CHECKIZHINX-NEXT: # %bb.1:
|
|
; CHECKIZHINX-NEXT: mv a2, a3
|
|
; CHECKIZHINX-NEXT: .LBB8_2:
|
|
; CHECKIZHINX-NEXT: mv a0, a2
|
|
; CHECKIZHINX-NEXT: ret
|
|
;
|
|
; CHECKIZFHMIN-LABEL: select_icmp_slt:
|
|
; CHECKIZFHMIN: # %bb.0:
|
|
; CHECKIZFHMIN-NEXT: blt a0, a1, .LBB8_2
|
|
; CHECKIZFHMIN-NEXT: # %bb.1:
|
|
; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
|
|
; CHECKIZFHMIN-NEXT: .LBB8_2:
|
|
; CHECKIZFHMIN-NEXT: ret
|
|
;
|
|
; CHECKIZHINXMIN-LABEL: select_icmp_slt:
|
|
; CHECKIZHINXMIN: # %bb.0:
|
|
; CHECKIZHINXMIN-NEXT: blt a0, a1, .LBB8_2
|
|
; CHECKIZHINXMIN-NEXT: # %bb.1:
|
|
; CHECKIZHINXMIN-NEXT: mv a2, a3
|
|
; CHECKIZHINXMIN-NEXT: .LBB8_2:
|
|
; CHECKIZHINXMIN-NEXT: mv a0, a2
|
|
; CHECKIZHINXMIN-NEXT: ret
|
|
%1 = icmp slt i32 %a, %b
|
|
%2 = select i1 %1, half %c, half %d
|
|
ret half %2
|
|
}
|
|
|
|
define half @select_icmp_sle(i32 signext %a, i32 signext %b, half %c, half %d) {
|
|
; CHECK-LABEL: select_icmp_sle:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: bge a1, a0, .LBB9_2
|
|
; CHECK-NEXT: # %bb.1:
|
|
; CHECK-NEXT: fmv.h fa0, fa1
|
|
; CHECK-NEXT: .LBB9_2:
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECKIZHINX-LABEL: select_icmp_sle:
|
|
; CHECKIZHINX: # %bb.0:
|
|
; CHECKIZHINX-NEXT: bge a1, a0, .LBB9_2
|
|
; CHECKIZHINX-NEXT: # %bb.1:
|
|
; CHECKIZHINX-NEXT: mv a2, a3
|
|
; CHECKIZHINX-NEXT: .LBB9_2:
|
|
; CHECKIZHINX-NEXT: mv a0, a2
|
|
; CHECKIZHINX-NEXT: ret
|
|
;
|
|
; CHECKIZFHMIN-LABEL: select_icmp_sle:
|
|
; CHECKIZFHMIN: # %bb.0:
|
|
; CHECKIZFHMIN-NEXT: bge a1, a0, .LBB9_2
|
|
; CHECKIZFHMIN-NEXT: # %bb.1:
|
|
; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
|
|
; CHECKIZFHMIN-NEXT: .LBB9_2:
|
|
; CHECKIZFHMIN-NEXT: ret
|
|
;
|
|
; CHECKIZHINXMIN-LABEL: select_icmp_sle:
|
|
; CHECKIZHINXMIN: # %bb.0:
|
|
; CHECKIZHINXMIN-NEXT: bge a1, a0, .LBB9_2
|
|
; CHECKIZHINXMIN-NEXT: # %bb.1:
|
|
; CHECKIZHINXMIN-NEXT: mv a2, a3
|
|
; CHECKIZHINXMIN-NEXT: .LBB9_2:
|
|
; CHECKIZHINXMIN-NEXT: mv a0, a2
|
|
; CHECKIZHINXMIN-NEXT: ret
|
|
%1 = icmp sle i32 %a, %b
|
|
%2 = select i1 %1, half %c, half %d
|
|
ret half %2
|
|
}
|
|
|
|
define half @select_icmp_slt_one(i32 signext %a) {
|
|
; CHECK-LABEL: select_icmp_slt_one:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: slti a0, a0, 1
|
|
; CHECK-NEXT: fcvt.h.w fa0, a0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECKIZHINX-LABEL: select_icmp_slt_one:
|
|
; CHECKIZHINX: # %bb.0:
|
|
; CHECKIZHINX-NEXT: slti a0, a0, 1
|
|
; CHECKIZHINX-NEXT: fcvt.h.w a0, a0
|
|
; CHECKIZHINX-NEXT: ret
|
|
;
|
|
; CHECKIZFHMIN-LABEL: select_icmp_slt_one:
|
|
; CHECKIZFHMIN: # %bb.0:
|
|
; CHECKIZFHMIN-NEXT: slti a0, a0, 1
|
|
; CHECKIZFHMIN-NEXT: fcvt.s.w fa5, a0
|
|
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
|
|
; CHECKIZFHMIN-NEXT: ret
|
|
;
|
|
; CHECKIZHINXMIN-LABEL: select_icmp_slt_one:
|
|
; CHECKIZHINXMIN: # %bb.0:
|
|
; CHECKIZHINXMIN-NEXT: slti a0, a0, 1
|
|
; CHECKIZHINXMIN-NEXT: fcvt.s.w a0, a0
|
|
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
|
|
; CHECKIZHINXMIN-NEXT: ret
|
|
%1 = icmp slt i32 %a, 1
|
|
%2 = select i1 %1, half 1.000000e+00, half 0.000000e+00
|
|
ret half %2
|
|
}
|
|
|
|
define half @select_icmp_sgt_zero(i32 signext %a) {
|
|
; CHECK-LABEL: select_icmp_sgt_zero:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: slti a0, a0, 1
|
|
; CHECK-NEXT: fcvt.h.w fa0, a0
|
|
; CHECK-NEXT: ret
|
|
;
|
|
; CHECKIZHINX-LABEL: select_icmp_sgt_zero:
|
|
; CHECKIZHINX: # %bb.0:
|
|
; CHECKIZHINX-NEXT: slti a0, a0, 1
|
|
; CHECKIZHINX-NEXT: fcvt.h.w a0, a0
|
|
; CHECKIZHINX-NEXT: ret
|
|
;
|
|
; CHECKIZFHMIN-LABEL: select_icmp_sgt_zero:
|
|
; CHECKIZFHMIN: # %bb.0:
|
|
; CHECKIZFHMIN-NEXT: slti a0, a0, 1
|
|
; CHECKIZFHMIN-NEXT: fcvt.s.w fa5, a0
|
|
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
|
|
; CHECKIZFHMIN-NEXT: ret
|
|
;
|
|
; CHECKIZHINXMIN-LABEL: select_icmp_sgt_zero:
|
|
; CHECKIZHINXMIN: # %bb.0:
|
|
; CHECKIZHINXMIN-NEXT: slti a0, a0, 1
|
|
; CHECKIZHINXMIN-NEXT: fcvt.s.w a0, a0
|
|
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
|
|
; CHECKIZHINXMIN-NEXT: ret
|
|
%1 = icmp sgt i32 %a, 0
|
|
%2 = select i1 %1, half 0.000000e+00, half 1.000000e+00
|
|
ret half %2
|
|
}
|