derek.holloway
7502bf64a4
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193 lines
6.8 KiB
LLVM
193 lines
6.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: not llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s 2>&1 \
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; RUN: | FileCheck %s -check-prefixes=RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV64
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declare void @inspect(...)
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; Tests stack addressing when stack-size doesn't fit in 32bit.
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; Should fail on 32-bit systems.
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; RV32: LLVM ERROR: Frame offsets outside of the signed 32-bit range not supported on RV32
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define void @stack_bigger_than_32bit() {
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; RV64-LABEL: stack_bigger_than_32bit:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -2032
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; RV64-NEXT: .cfi_def_cfa_offset 2032
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; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: lui a0, 524288
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; RV64-NEXT: addiw a0, a0, -2000
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; RV64-NEXT: sub sp, sp, a0
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; RV64-NEXT: .cfi_def_cfa_offset 2147483680
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; RV64-NEXT: li a0, 1
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; RV64-NEXT: slli a0, a0, 31
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; RV64-NEXT: addi a0, a0, 8
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; RV64-NEXT: add a0, sp, a0
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; RV64-NEXT: addi a1, sp, 8
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; RV64-NEXT: call inspect
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; RV64-NEXT: lui a0, 524288
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; RV64-NEXT: addiw a0, a0, -2000
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; RV64-NEXT: add sp, sp, a0
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; RV64-NEXT: .cfi_def_cfa_offset 2032
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; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
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; RV64-NEXT: .cfi_restore ra
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; RV64-NEXT: addi sp, sp, 2032
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; RV64-NEXT: .cfi_def_cfa_offset 0
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; RV64-NEXT: ret
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%p1 = alloca [2 x i64], align 1
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%p2 = alloca [2147483648 x i8], align 1
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call void (...) @inspect(ptr %p1, ptr %p2)
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ret void
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}
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; Same as previous test, just uses frame-pointer to access fixed objects.
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define void @vla(i64 %n) {
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; RV64-LABEL: vla:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -2032
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; RV64-NEXT: .cfi_def_cfa_offset 2032
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; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
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; RV64-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: .cfi_offset s0, -16
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; RV64-NEXT: addi s0, sp, 2032
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; RV64-NEXT: .cfi_def_cfa s0, 0
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; RV64-NEXT: lui a1, 524288
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; RV64-NEXT: addiw a1, a1, -1984
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; RV64-NEXT: sub sp, sp, a1
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; RV64-NEXT: slli a0, a0, 2
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; RV64-NEXT: addi a0, a0, 15
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; RV64-NEXT: andi a0, a0, -16
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; RV64-NEXT: sub a2, sp, a0
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; RV64-NEXT: mv sp, a2
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; RV64-NEXT: addi a0, s0, -40
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; RV64-NEXT: li a1, 1
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; RV64-NEXT: slli a1, a1, 31
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; RV64-NEXT: addi a1, a1, 40
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; RV64-NEXT: sub a1, s0, a1
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; RV64-NEXT: call inspect
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; RV64-NEXT: addi sp, s0, -2032
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; RV64-NEXT: .cfi_def_cfa sp, 2032
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; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
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; RV64-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
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; RV64-NEXT: .cfi_restore ra
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; RV64-NEXT: .cfi_restore s0
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; RV64-NEXT: addi sp, sp, 2032
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; RV64-NEXT: .cfi_def_cfa_offset 0
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; RV64-NEXT: ret
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%p1 = alloca [2 x i64], align 1
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%p2 = alloca [2147483648 x i8], align 1
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%vla = alloca i32, i64 %n, align 4
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call void (...) @inspect(ptr %p1, ptr %p2, ptr %vla)
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ret void
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}
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define void @rvv_frame_obj() {
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; RV64-LABEL: rvv_frame_obj:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -2032
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; RV64-NEXT: .cfi_def_cfa_offset 2032
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; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: lui a0, 524288
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; RV64-NEXT: addiw a0, a0, -1984
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; RV64-NEXT: sub sp, sp, a0
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; RV64-NEXT: .cfi_def_cfa_offset 2147483696
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: slli a0, a0, 1
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; RV64-NEXT: sub sp, sp, a0
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; RV64-NEXT: .cfi_escape 0x0f, 0x11, 0x72, 0x00, 0x11, 0xb0, 0x80, 0x80, 0x80, 0x08, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 2147483696 + 2 * vlenb
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; RV64-NEXT: li a0, 1
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; RV64-NEXT: slli a0, a0, 31
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; RV64-NEXT: addi a0, a0, 8
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; RV64-NEXT: add a0, sp, a0
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; RV64-NEXT: addi a1, sp, 8
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; RV64-NEXT: csrr a2, vlenb
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; RV64-NEXT: add a2, sp, a2
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; RV64-NEXT: li a3, 1
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; RV64-NEXT: slli a3, a3, 31
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; RV64-NEXT: addi a3, a3, 32
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; RV64-NEXT: add a2, a2, a3
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; RV64-NEXT: li a3, 1
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; RV64-NEXT: slli a3, a3, 31
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; RV64-NEXT: addi a3, a3, 32
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; RV64-NEXT: add a3, sp, a3
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; RV64-NEXT: call inspect
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: slli a0, a0, 1
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; RV64-NEXT: add sp, sp, a0
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; RV64-NEXT: .cfi_def_cfa sp, 2032
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; RV64-NEXT: lui a0, 524288
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; RV64-NEXT: addiw a0, a0, -1984
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; RV64-NEXT: add sp, sp, a0
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; RV64-NEXT: .cfi_def_cfa_offset 2032
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; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
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; RV64-NEXT: .cfi_restore ra
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; RV64-NEXT: addi sp, sp, 2032
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; RV64-NEXT: .cfi_def_cfa_offset 0
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; RV64-NEXT: ret
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%p1 = alloca [2 x i64], align 1
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%p2 = alloca [2147483648 x i8], align 1
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%vector1 = alloca <vscale x 1 x i64>, align 1
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%vector2 = alloca <vscale x 1 x i64>, align 1
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call void (...) @inspect(ptr %p1, ptr %p2, ptr %vector1, ptr %vector2)
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ret void
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}
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define <vscale x 1 x i64> @rvv_spill(<vscale x 1 x i64> %vector) {
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; RV64-LABEL: rvv_spill:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -2032
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; RV64-NEXT: .cfi_def_cfa_offset 2032
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; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: lui a0, 524288
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; RV64-NEXT: addiw a0, a0, -1968
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; RV64-NEXT: sub sp, sp, a0
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; RV64-NEXT: .cfi_def_cfa_offset 2147483712
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: sub sp, sp, a0
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; RV64-NEXT: .cfi_escape 0x0f, 0x11, 0x72, 0x00, 0x11, 0xc0, 0x80, 0x80, 0x80, 0x08, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 2147483712 + 1 * vlenb
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; RV64-NEXT: li a0, 1
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; RV64-NEXT: slli a0, a0, 31
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; RV64-NEXT: addi a0, a0, 48
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; RV64-NEXT: add a0, sp, a0
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; RV64-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
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; RV64-NEXT: #APP
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; RV64-NEXT: #NO_APP
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; RV64-NEXT: li a0, 1
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; RV64-NEXT: slli a0, a0, 31
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; RV64-NEXT: addi a0, a0, 24
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; RV64-NEXT: add a0, sp, a0
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; RV64-NEXT: addi a1, sp, 24
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; RV64-NEXT: call inspect
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; RV64-NEXT: li a0, 1
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; RV64-NEXT: slli a0, a0, 31
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; RV64-NEXT: addi a0, a0, 48
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; RV64-NEXT: add a0, sp, a0
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; RV64-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: add sp, sp, a0
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; RV64-NEXT: .cfi_def_cfa sp, 2032
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; RV64-NEXT: lui a0, 524288
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; RV64-NEXT: addiw a0, a0, -1968
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; RV64-NEXT: add sp, sp, a0
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; RV64-NEXT: .cfi_def_cfa_offset 2032
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; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
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; RV64-NEXT: .cfi_restore ra
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; RV64-NEXT: addi sp, sp, 2032
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; RV64-NEXT: .cfi_def_cfa_offset 0
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; RV64-NEXT: ret
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call void asm sideeffect "",
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"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
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%p1 = alloca [2 x i64], align 1
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%p2 = alloca [2147483648 x i8], align 1
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call void (...) @inspect(ptr %p1, ptr %p2)
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ret <vscale x 1 x i64> %vector
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}
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