derek.holloway
7502bf64a4
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249 lines
6.4 KiB
LLVM
249 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=sparc | FileCheck %s
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; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=CHECK64
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define i32 @test(i32 %a) nounwind {
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; CHECK-LABEL: test:
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; CHECK: ! %bb.0: ! %entry
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; CHECK-NEXT: andcc %o0, 1, %g0
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; CHECK-NEXT: bne .LBB0_2
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; CHECK-NEXT: nop
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; CHECK-NEXT: ! %bb.1: ! %if.end
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; CHECK-NEXT: retl
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; CHECK-NEXT: mov 2, %o0
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; CHECK-NEXT: .LBB0_2: ! %if.then
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; CHECK-NEXT: retl
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; CHECK-NEXT: mov 1, %o0
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;
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; CHECK64-LABEL: test:
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; CHECK64: ! %bb.0: ! %entry
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; CHECK64-NEXT: andcc %o0, 1, %g0
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; CHECK64-NEXT: bne %icc, .LBB0_2
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; CHECK64-NEXT: nop
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; CHECK64-NEXT: ! %bb.1: ! %if.end
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; CHECK64-NEXT: retl
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; CHECK64-NEXT: mov 2, %o0
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; CHECK64-NEXT: .LBB0_2: ! %if.then
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; CHECK64-NEXT: retl
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; CHECK64-NEXT: mov 1, %o0
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entry:
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%and = and i32 %a, 1
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%tobool = icmp eq i32 %and, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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ret i32 1
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if.end:
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ret i32 2
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}
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; Same as above, with select.
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define i32 @test_select(i32 %a) nounwind {
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; CHECK-LABEL: test_select:
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; CHECK: ! %bb.0:
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; CHECK-NEXT: andcc %o0, 1, %g0
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; CHECK-NEXT: be .LBB1_2
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; CHECK-NEXT: nop
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; CHECK-NEXT: ! %bb.1:
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; CHECK-NEXT: retl
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; CHECK-NEXT: mov 2, %o0
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: retl
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; CHECK-NEXT: mov 1, %o0
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;
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; CHECK64-LABEL: test_select:
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; CHECK64: ! %bb.0:
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; CHECK64-NEXT: andcc %o0, 1, %g0
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; CHECK64-NEXT: mov 2, %o0
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; CHECK64-NEXT: retl
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; CHECK64-NEXT: move %icc, 1, %o0
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%and = and i32 %a, 1
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%tobool = icmp eq i32 %and, 0
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%ret = select i1 %tobool, i32 1, i32 2
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ret i32 %ret
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}
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; No instruction can be changed to set ICC
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define i32 @no_candidate(i32 %a) nounwind {
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; CHECK-LABEL: no_candidate:
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; CHECK: ! %bb.0: ! %entry
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; CHECK-NEXT: cmp %o0, 0
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; CHECK-NEXT: be .LBB2_2
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; CHECK-NEXT: nop
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; CHECK-NEXT: ! %bb.1: ! %if.then
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; CHECK-NEXT: retl
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; CHECK-NEXT: mov 1, %o0
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; CHECK-NEXT: .LBB2_2: ! %if.end
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; CHECK-NEXT: retl
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; CHECK-NEXT: mov 2, %o0
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;
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; CHECK64-LABEL: no_candidate:
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; CHECK64: ! %bb.0: ! %entry
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; CHECK64-NEXT: cmp %o0, 0
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; CHECK64-NEXT: be %icc, .LBB2_2
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; CHECK64-NEXT: nop
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; CHECK64-NEXT: ! %bb.1: ! %if.then
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; CHECK64-NEXT: retl
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; CHECK64-NEXT: mov 1, %o0
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; CHECK64-NEXT: .LBB2_2: ! %if.end
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; CHECK64-NEXT: retl
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; CHECK64-NEXT: mov 2, %o0
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entry:
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%tobool = icmp eq i32 %a, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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ret i32 1
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if.end:
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ret i32 2
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}
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; Defining instruction and compare not in same block
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define i32 @not_same_block(i32 %a) nounwind {
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; CHECK-LABEL: not_same_block:
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; CHECK: ! %bb.0: ! %entry
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; CHECK-NEXT: and %o0, 1, %o0
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; CHECK-NEXT: .LBB3_1: ! %if.then
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; CHECK-NEXT: ! =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmp %o0, 0
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; CHECK-NEXT: bne .LBB3_1
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; CHECK-NEXT: nop
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; CHECK-NEXT: ! %bb.2: ! %if.end
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; CHECK-NEXT: retl
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; CHECK-NEXT: mov 2, %o0
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;
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; CHECK64-LABEL: not_same_block:
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; CHECK64: ! %bb.0: ! %entry
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; CHECK64-NEXT: and %o0, 1, %o0
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; CHECK64-NEXT: .LBB3_1: ! %if.then
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; CHECK64-NEXT: ! =>This Inner Loop Header: Depth=1
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; CHECK64-NEXT: cmp %o0, 0
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; CHECK64-NEXT: bne %icc, .LBB3_1
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; CHECK64-NEXT: nop
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; CHECK64-NEXT: ! %bb.2: ! %if.end
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; CHECK64-NEXT: retl
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; CHECK64-NEXT: mov 2, %o0
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entry:
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%and = and i32 %a, 1
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br label %if.then
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if.then:
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%tobool = icmp eq i32 %and, 0
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br i1 %tobool, label %if.end, label %if.then
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ret i32 1
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if.end:
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ret i32 2
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}
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; Compare instruction is not checking equality
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define i32 @not_equality(i32 %a) nounwind {
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; CHECK-LABEL: not_equality:
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; CHECK: ! %bb.0: ! %entry
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; CHECK-NEXT: add %o0, -1, %o1
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; CHECK-NEXT: cmp %o1, 0
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; CHECK-NEXT: bl .LBB4_2
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; CHECK-NEXT: nop
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; CHECK-NEXT: ! %bb.1: ! %entry
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; CHECK-NEXT: mov %o1, %o0
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; CHECK-NEXT: .LBB4_2: ! %entry
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; CHECK-NEXT: retl
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; CHECK-NEXT: nop
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;
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; CHECK64-LABEL: not_equality:
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; CHECK64: ! %bb.0: ! %entry
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; CHECK64-NEXT: add %o0, -1, %o1
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; CHECK64-NEXT: cmp %o1, 0
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; CHECK64-NEXT: movl %icc, %o0, %o1
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; CHECK64-NEXT: retl
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; CHECK64-NEXT: mov %o1, %o0
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entry:
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%sub = sub i32 %a, 1
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%cmp = icmp slt i32 %sub, 0
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%cond = select i1 %cmp, i32 %a, i32 %sub
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ret i32 %cond
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}
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; Instruction that modifies ICC (call) between defining
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; and compare instruction.
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define i32 @call_between(i32 %a) nounwind {
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; CHECK-LABEL: call_between:
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; CHECK: ! %bb.0: ! %entry
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; CHECK-NEXT: save %sp, -96, %sp
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; CHECK-NEXT: and %i0, 1, %i1
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; CHECK-NEXT: call not_equality
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; CHECK-NEXT: mov %i1, %o0
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; CHECK-NEXT: cmp %i1, 0
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; CHECK-NEXT: be .LBB5_2
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; CHECK-NEXT: nop
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; CHECK-NEXT: ! %bb.1: ! %entry
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; CHECK-NEXT: mov %i1, %i0
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; CHECK-NEXT: .LBB5_2: ! %entry
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; CHECK-NEXT: ret
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; CHECK-NEXT: restore
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;
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; CHECK64-LABEL: call_between:
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; CHECK64: ! %bb.0: ! %entry
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; CHECK64-NEXT: save %sp, -176, %sp
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; CHECK64-NEXT: and %i0, 1, %i1
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; CHECK64-NEXT: call not_equality
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; CHECK64-NEXT: mov %i1, %o0
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; CHECK64-NEXT: cmp %i1, 0
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; CHECK64-NEXT: move %icc, %i0, %i1
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; CHECK64-NEXT: ret
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; CHECK64-NEXT: restore %g0, %i1, %o0
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entry:
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%and = and i32 %a, 1
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call i32 @not_equality(i32 %and)
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%cmp = icmp eq i32 %and, 0
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%cond = select i1 %cmp, i32 %a, i32 %and
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ret i32 %cond
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}
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; ICC is used in successor block.
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define i32 @icc_live_out(i32 %a) nounwind {
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; CHECK-LABEL: icc_live_out:
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; CHECK: ! %bb.0: ! %entry
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; CHECK-NEXT: andcc %o0, 1, %o1
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; CHECK-NEXT: bne .LBB6_4
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; CHECK-NEXT: nop
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; CHECK-NEXT: ! %bb.1: ! %case1
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; CHECK-NEXT: cmp %o1, 0
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; CHECK-NEXT: be .LBB6_3
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; CHECK-NEXT: nop
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; CHECK-NEXT: ! %bb.2: ! %case1
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; CHECK-NEXT: mov %o1, %o0
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; CHECK-NEXT: .LBB6_3: ! %case1
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; CHECK-NEXT: retl
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB6_4: ! %case2
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; CHECK-NEXT: retl
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; CHECK-NEXT: mov 2, %o0
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;
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; CHECK64-LABEL: icc_live_out:
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; CHECK64: ! %bb.0: ! %entry
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; CHECK64-NEXT: mov %o0, %o1
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; CHECK64-NEXT: andcc %o0, 1, %o0
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; CHECK64-NEXT: bne %icc, .LBB6_2
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; CHECK64-NEXT: nop
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; CHECK64-NEXT: ! %bb.1: ! %case1
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; CHECK64-NEXT: cmp %o0, 0
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; CHECK64-NEXT: retl
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; CHECK64-NEXT: move %icc, %o1, %o0
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; CHECK64-NEXT: .LBB6_2: ! %case2
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; CHECK64-NEXT: retl
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; CHECK64-NEXT: mov 2, %o0
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entry:
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%and = and i32 %a, 1
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%cmp = icmp eq i32 %and, 0
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br i1 %cmp, label %case1, label %case2
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case1:
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%cond = select i1 %cmp, i32 %a, i32 %and
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ret i32 %cond
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case2:
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ret i32 2
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}
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