derek.holloway
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70 lines
1.9 KiB
LLVM
70 lines
1.9 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
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; This tests that indirectbr instructions are lowered to switches. Currently we
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; just re-use the IndirectBrExpand Pass; it has its own IR-level test.
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; So this test just ensures that the pass gets run and we can lower indirectbr
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target triple = "wasm32"
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@test1.targets = constant [4 x ptr] [ptr blockaddress(@test1, %bb0),
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ptr blockaddress(@test1, %bb1),
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ptr blockaddress(@test1, %bb2),
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ptr blockaddress(@test1, %bb3)]
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; Just check the barest skeleton of the structure
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; CHECK-LABEL: test1:
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; CHECK: i32.load
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; CHECK: i32.load
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; CHECK: loop
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; CHECK: block
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; CHECK: block
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; CHECK: block
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; CHECK: block
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; CHECK: br_table ${{[^,]+}}, 1, 2, 0
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; CHECK: end_block
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; CHECK: end_block
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; CHECK: end_block
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; CHECK: end_block
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; CHECK: br
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; CHECK: end_loop
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; CHECK: end_function
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; CHECK: test1.targets:
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; CHECK-NEXT: .int32
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; CHECK-NEXT: .int32
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; CHECK-NEXT: .int32
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; CHECK-NEXT: .int32
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define void @test1(ptr readonly %p, ptr %sink) #0 {
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entry:
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%i0 = load i32, ptr %p
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%target.i0 = getelementptr [4 x ptr], ptr @test1.targets, i32 0, i32 %i0
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%target0 = load ptr, ptr %target.i0
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; Only a subset of blocks are viable successors here.
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indirectbr ptr %target0, [label %bb0, label %bb1]
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bb0:
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store volatile i32 0, ptr %sink
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br label %latch
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bb1:
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store volatile i32 1, ptr %sink
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br label %latch
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bb2:
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store volatile i32 2, ptr %sink
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br label %latch
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bb3:
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store volatile i32 3, ptr %sink
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br label %latch
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latch:
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%i.next = load i32, ptr %p
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%target.i.next = getelementptr [4 x ptr], ptr @test1.targets, i32 0, i32 %i.next
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%target.next = load ptr, ptr %target.i.next
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; A different subset of blocks are viable successors here.
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indirectbr ptr %target.next, [label %bb1, label %bb2]
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}
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