derek.holloway
7502bf64a4
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71 lines
3.0 KiB
TableGen
71 lines
3.0 KiB
TableGen
// RUN: llvm-tblgen -gen-asm-writer -I %S -I %p/../../include %s -o - | FileCheck %s
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include "Common/RegClassByHwModeCommon.td"
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def IsPtrY : Predicate<"Subtarget->isPtrY()">;
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defvar PtrX = DefaultMode;
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def PtrY : HwMode<[IsPtrY]>;
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// Define more restrictive subset classes to check that those are handled.
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def EvenXRegs : RegisterClass<"MyTarget", [i64], 64, (add X0, X2, X4, X6)>;
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def EvenYRegs : RegisterClass<"MyTarget", [i64], 64, (add Y0, Y2, Y4, Y6)>;
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def PtrRC : RegClassByHwMode<[PtrX, PtrY], [XRegs, YRegs]>;
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def EvenPtrRC : RegClassByHwMode<[PtrX, PtrY], [EvenXRegs, EvenYRegs]>;
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def NullReg : RegisterByHwMode<PtrRC, [PtrX, PtrY], [X0, Y0]>;
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def TEST_XREG : TestInstruction {
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let OutOperandList = (outs XRegs:$dst);
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let InOperandList = (ins XRegs:$src);
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let AsmString = "t_x $dst, $src";
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let opcode = 0;
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}
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def TEST_PTR : TestInstruction {
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let OutOperandList = (outs PtrRC:$dst);
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let InOperandList = (ins PtrRC:$src);
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let AsmString = "t_ptr $dst, $src";
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let opcode = 0;
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}
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def MY_T_X : InstAlias<"t_x $src", (TEST_XREG X0, XRegs:$src)>;
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def MY_T_X_EVEN : InstAlias<"t_x.even $src", (TEST_XREG EvenXRegs:$dst, EvenXRegs:$src)>;
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def MY_T_PTR : InstAlias<"t_ptr $src", (TEST_PTR NullReg, PtrRC:$src)>;
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def MY_T_PTR_EVEN : InstAlias<"t_ptr.even $src", (TEST_PTR EvenPtrRC:$dst, EvenPtrRC:$src)>;
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// CHECK-LABEL: static const AliasPatternCond Conds[] = {
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// CHECK-NEXT: // (TEST_PTR NullReg, PtrRC:$src) - 0
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// CHECK-NEXT: {AliasPatternCond::K_Custom, 1/*NullReg*/},
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// CHECK-NEXT: {AliasPatternCond::K_RegClassByHwMode, MyTarget::PtrRC},
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// CHECK-NEXT: // (TEST_PTR EvenPtrRC:$dst, EvenPtrRC:$src) - 2
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// CHECK-NEXT: {AliasPatternCond::K_RegClassByHwMode, MyTarget::EvenPtrRC},
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// CHECK-NEXT: {AliasPatternCond::K_RegClassByHwMode, MyTarget::EvenPtrRC},
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// CHECK-NEXT: // (TEST_XREG X0, XRegs:$src) - 4
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// CHECK-NEXT: {AliasPatternCond::K_Reg, MyTarget::X0},
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// CHECK-NEXT: {AliasPatternCond::K_RegClass, MyTarget::XRegsRegClassID},
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// CHECK-NEXT: // (TEST_XREG EvenXRegs:$dst, EvenXRegs:$src) - 6
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// CHECK-NEXT: {AliasPatternCond::K_RegClass, MyTarget::EvenXRegsRegClassID},
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// CHECK-NEXT: {AliasPatternCond::K_RegClass, MyTarget::EvenXRegsRegClassID},
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// CHECK-NEXT: };
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// CHECK-LABEL: static bool MyTargetInstPrinterValidateMCOperand(const MCOperand &MCOp,
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// CHECK-NEXT: const MCSubtargetInfo &STI,
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// CHECK-NEXT: unsigned PredicateIndex) {
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// CHECK-NEXT: switch (PredicateIndex) {
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// CHECK-NEXT: default:
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// CHECK-NEXT: llvm_unreachable("Unknown MCOperandPredicate kind");
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// CHECK-NEXT: break;
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// CHECK-NEXT: case 1: {
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// CHECK-NEXT: return MCOp.isReg() && MCOp.getReg() == MyTarget::RegisterByHwMode::getNullReg(STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo));
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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def MyTargetISA : InstrInfo;
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def MyTargetAsmWriter : AsmWriter {
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int PassSubtarget = 1;
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}
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def MyTarget : Target {
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let InstructionSet = MyTargetISA;
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let AssemblyWriters = [MyTargetAsmWriter];
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}
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