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152 lines
6.2 KiB
C++
152 lines
6.2 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of libcu++, the C++ Standard Library for your entire system,
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// under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
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//
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//===----------------------------------------------------------------------===//
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// MIT License
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//
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// Modifications Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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#ifndef _LIBCUDACXX___BIT_INTEGRAL_H
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#define _LIBCUDACXX___BIT_INTEGRAL_H
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#include <cuda/std/detail/__config>
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#if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC)
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# pragma GCC system_header
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#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG)
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# pragma clang system_header
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#elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC)
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# pragma system_header
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#endif // no system header
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// #include <cuda/__ptx/instructions/bfind.h>
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// #include <cuda/__ptx/instructions/shl.h>
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// #include <cuda/__ptx/instructions/shr.h>
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#include <cuda/std/__algorithm/max.h>
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#include <cuda/std/__bit/countl.h>
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#include <cuda/std/__concepts/concept_macros.h>
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#include <cuda/std/__type_traits/conditional.h>
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#include <cuda/std/__type_traits/is_constant_evaluated.h>
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#include <cuda/std/__type_traits/is_unsigned_integer.h>
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#include <cuda/std/cstdint>
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#include <cuda/std/limits>
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_LIBCUDACXX_BEGIN_NAMESPACE_STD
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template <class _Tp>
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_LIBCUDACXX_HIDE_FROM_ABI constexpr uint32_t __bit_log2(_Tp __t) noexcept
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{
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// Note(HIP/AMD): bfind uses ptx which is not available for AMD hardware
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/*
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if (!_CUDA_VSTD::__cccl_default_is_constant_evaluated())
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{
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if constexpr (sizeof(_Tp) <= 8)
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{
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using _Up [[maybe_unused]] = _If<sizeof(_Tp) <= 4, uint32_t, uint64_t>;
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NV_IF_TARGET_LIBHIPCXX(NV_IS_DEVICE_LIBHIPCXX, (return _CUDA_VPTX::bfind(static_cast<_Up>(__t));))
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}
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else
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{
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NV_IF_TARGET_LIBHIPCXX(NV_IS_DEVICE_LIBHIPCXX,
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(auto __high = _CUDA_VPTX::bfind(static_cast<uint64_t>(__t >> 64));
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return __high == ~uint32_t{0} ? _CUDA_VPTX::bfind(static_cast<uint64_t>(__t)) : __high + 64;))
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}
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}
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*/
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return numeric_limits<_Tp>::digits - 1 - _CUDA_VSTD::countl_zero(__t);
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}
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_CCCL_TEMPLATE(class _Tp)
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_CCCL_REQUIRES(_CCCL_TRAIT(_CUDA_VSTD::__cccl_is_unsigned_integer, _Tp))
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_CCCL_NODISCARD _LIBCUDACXX_HIDE_FROM_ABI constexpr int bit_width(_Tp __t) noexcept
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{
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// if __t == 0, __bit_log2(0) returns 0xFFFFFFFF. Since unsigned overflow is well-defined, the result is -1 + 1 = 0
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auto __ret = _CUDA_VSTD::__bit_log2(__t) + 1;
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_CCCL_BUILTIN_ASSUME(__ret <= numeric_limits<_Tp>::digits);
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return static_cast<int>(__ret);
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}
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_CCCL_TEMPLATE(class _Tp)
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_CCCL_REQUIRES(_CCCL_TRAIT(_CUDA_VSTD::__cccl_is_unsigned_integer, _Tp))
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_CCCL_NODISCARD _LIBCUDACXX_HIDE_FROM_ABI constexpr _Tp bit_ceil(_Tp __t) noexcept
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{
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using _Up = _If<sizeof(_Tp) <= 4, uint32_t, _Tp>;
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_CCCL_ASSERT(__t <= numeric_limits<_Tp>::max() / 2, "bit_ceil overflow");
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// if __t == 0, __t - 1 == 0xFFFFFFFF, bit_width(0xFFFFFFFF) returns 32
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auto __width = _CUDA_VSTD::bit_width(static_cast<_Up>(__t) - 1);
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if constexpr (sizeof(_Tp) <= 8)
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{
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// Note(HIP/AMD): bfind uses ptx which is not available for AMD hardware
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/*
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if (!_CUDA_VSTD::__cccl_default_is_constant_evaluated())
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{
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// CUDA right shift (ptx::shr) returns 0 if the right operand is larger than the number of bits of the type
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// The result is computed as max(1, bit_width(__t - 1)) because it is more efficient than the ternary operator
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NV_IF_TARGET_LIBHIPCXX(NV_IS_DEVICE_LIBHIPCXX, //
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(auto __shift = _CUDA_VPTX::shl(_Up{1}, __width); // 2^(ceil(log2(__t - 1)))
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auto __ret = static_cast<_Tp>(_CUDA_VSTD::max(_Up{1}, __shift)); //
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_CCCL_BUILTIN_ASSUME(__ret >= __t);
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return __ret;))
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}
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*/
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}
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auto __ret = static_cast<_Tp>(__t <= 1 ? _Up{1} : _Up{1} << __width);
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_CCCL_BUILTIN_ASSUME(__ret >= __t);
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return __ret;
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}
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_CCCL_TEMPLATE(class _Tp)
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_CCCL_REQUIRES(_CCCL_TRAIT(_CUDA_VSTD::__cccl_is_unsigned_integer, _Tp))
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_CCCL_NODISCARD _LIBCUDACXX_HIDE_FROM_ABI constexpr _Tp bit_floor(_Tp __t) noexcept
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{
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using _Up = _If<sizeof(_Tp) <= 4, uint32_t, _Tp>;
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auto __log2 = _CUDA_VSTD::__bit_log2(static_cast<_Up>(__t));
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// __bit_log2 returns 0xFFFFFFFF if __t == 0
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if constexpr (sizeof(_Tp) <= 8)
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{
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// Note(HIP/AMD): bfind uses ptx which is not available for AMD hardware
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/*
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if (!_CUDA_VSTD::__cccl_default_is_constant_evaluated())
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{
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// CUDA left shift (ptx::shl) returns 0 if the right operand is larger than the number of bits of the type
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// -> the result is 0 if __t == 0
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NV_IF_TARGET_LIBHIPCXX(NV_IS_DEVICE_LIBHIPCXX, //
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(auto __ret = static_cast<_Tp>(_CUDA_VPTX::shl(_Up{1}, __log2)); // 2^(log2(t))
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_CCCL_BUILTIN_ASSUME(__ret >= __t / 2 && __ret <= __t);
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return __ret;))
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}
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*/
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}
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auto __ret = static_cast<_Tp>(__t == 0 ? _Up{0} : _Up{1} << __log2);
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_CCCL_BUILTIN_ASSUME(__ret >= __t / 2 && __ret <= __t);
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return __ret;
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}
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_LIBCUDACXX_END_NAMESPACE_STD
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#endif // _LIBCUDACXX___BIT_INTEGRAL_H
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