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132 lines
3.6 KiB
Markdown
132 lines
3.6 KiB
Markdown
# Change Log for hipSPARSELt
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Full documentation for hipSPARSELt is available at [rocm.docs.amd.com/projects/hipSPARSELt](https://rocm.docs.amd.com/projects/hipSPARSELt/en/latest/index.html).
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## hipSPARSELt 0.2.9 for ROCm 7.14
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### Added
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* Support for the following data type combinations for the LLVM target gfx942:
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* FP8_FNUZ(E4M3_FNUZ) inputs, F32 output, and F32 Matrix Core accumulation.
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* BF8_FNUZ(E5M2_FNUZ) inputs, F32 output, and F32 Matrix Core accumulation.
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## hipSPARSELt 0.2.8 for ROCm 7.13
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### Added
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* CTest and test categories support (`--smoke`, `--pre_checkin`, and `--nightly`).
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### Optimized
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* Provided more kernels for the FP16, BF16 and Int8 datatypes.
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* Improved the performance of the `HIPSPARSELT_PRUNE_SPMMA_TILE` function.
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### Resolved issues
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* Fixed incorrect behavior when retrieving the PCI chip ID.
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* Fixed LDS out-of-bounds read in `prune_tile_kernel`.
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* Fixed out-of-bounds access for compress function test cases.
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* Fixed missing null terminator in the return value of `hipsparseLtGetArchName()`
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* Fixed incorrect CPU result when `bias_type` is BF16 for spmm test cases.
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* Fixed double-free issue in example code: `example_prune_strip`.
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* Fixed symbol interposition in the hipSPARSELt library.
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## hipSPARSELt 0.2.7 for ROCm 7.12
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### Added
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* Support for the following data type combinations for the LLVM target gfx942/gfx950:
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* `INT8` inputs, `INT32` output, and `INT32` Matrix Core accumulation.
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## hipSPARSELt 0.2.6 for ROCm 7.2.0
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### Optimized
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* Provided more kernels for the `FP16` and `FP8(E4M3)` data types.
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## hipSPARSELt 0.2.5 for ROCm 7.1.0
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### Changed
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* Changed the behavior of the Relu activation.
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### Optimized
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* Provided more kernels for the `FP16` and `BF16` data types.
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## hipSPARSELt 0.2.4 for ROCm 7.0.0
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### Added
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* Support for the LLVM target gfx950.
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* Support for the following data type combinations for the LLVM target gfx950:
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* FP8(E4M3) inputs, F32 output, and F32 Matrix Core accumulation.
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* BF8(E5M2) inputs, F32 output, and F32 Matrix Core accumulation.
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* Support for ROC-TX if `HIPSPARSELT_ENABLE_MARKER=1` is set.
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* Support for the cuSPARSELt v0.6.3 backend.
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### Optimized
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* Improved the library loading time.
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* Provided more kernels for FP16 datatype.
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### Removed
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* Support for LLVM targets gfx940 and gfx941 has been removed.
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* `hipsparseLtDatatype_t` has been removed.
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## hipSPARSELt 0.2.3 for ROCm 6.4.0
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### Added
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* Support for alpha vector scaling.
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### Changed
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* Changed the check mechanism of the inputs when is using alpha vector scaling.
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## hipSPARSELt 0.2.2 for ROCm 6.3.0
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### Added
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* Support for a new data type combination: INT8 inputs, BF16 output, and INT32 Matrix Core accumulation.
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* Support for row-major memory order (HIPSPARSE_ORDER_ROW).
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### Changed
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* Changed the default compiler to amdclang++.
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### Upcoming changes
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* hipsparseLtDatatype_t is deprecated and will be removed in the next major release of ROCm. hipDataType should be used instead.
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## hipSPARSELt 0.2.1 for ROCm 6.2
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### Changed
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* Refined test cases
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## hipSPARSELt 0.2.0 for ROCm 6.1
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### Changes
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* Support Matrix B is a Structured Sparsity Matrix.
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## hipSPARSELt 0.1.0 for ROCm 6.0
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### Changes
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* Enabled hipSPARSELt APIs
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* Support for:
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* gfx940, gfx941, and gfx942 platforms
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* FP16, BF16, and INT8 problem types
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* ReLU, GELU, abs, sigmod, and tanh activation
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* GELU scaling
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* Bias vectors
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* cuSPARSELt v0.4 backend
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* Integrated with Tensile Lite kernel generator
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* Support for batched computation (single sparse x multiple dense and multiple sparse x single dense)
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* GoogleTest: hipsparselt-test
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* `hipsparselt-bench` benchmarking tool
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* Sample apps: `example_spmm_strided_batched`, `example_prune`, `example_compress`
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