derek.holloway
7502bf64a4
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196 lines
8.8 KiB
C
196 lines
8.8 KiB
C
// RUN: %clang_cc1 -triple arm64-apple-darwin -target-feature +neon -flax-vector-conversions=none \
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// RUN: -disable-O0-optnone -emit-llvm -o - %s \
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// RUN: | opt -S -passes=mem2reg | FileCheck %s
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// REQUIRES: aarch64-registered-target || arm-registered-target
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#include <arm_neon.h>
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// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_u8(i8 noundef %a, <8 x i8> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7
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// CHECK: ret <8 x i8> [[VSET_LANE]]
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uint8x8_t test_vset_lane_u8(uint8_t a, uint8x8_t b) {
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return vset_lane_u8(a, b, 7);
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}
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// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_u16(i16 noundef %a, <4 x i16> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> %b, i16 %a, i32 3
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// CHECK: ret <4 x i16> [[VSET_LANE]]
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uint16x4_t test_vset_lane_u16(uint16_t a, uint16x4_t b) {
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return vset_lane_u16(a, b, 3);
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}
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// CHECK-LABEL: define{{.*}} <2 x i32> @test_vset_lane_u32(i32 noundef %a, <2 x i32> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i32> %b, i32 %a, i32 1
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// CHECK: ret <2 x i32> [[VSET_LANE]]
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uint32x2_t test_vset_lane_u32(uint32_t a, uint32x2_t b) {
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return vset_lane_u32(a, b, 1);
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}
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// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_s8(i8 noundef %a, <8 x i8> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7
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// CHECK: ret <8 x i8> [[VSET_LANE]]
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int8x8_t test_vset_lane_s8(int8_t a, int8x8_t b) {
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return vset_lane_s8(a, b, 7);
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}
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// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_s16(i16 noundef %a, <4 x i16> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> %b, i16 %a, i32 3
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// CHECK: ret <4 x i16> [[VSET_LANE]]
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int16x4_t test_vset_lane_s16(int16_t a, int16x4_t b) {
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return vset_lane_s16(a, b, 3);
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}
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// CHECK-LABEL: define{{.*}} <2 x i32> @test_vset_lane_s32(i32 noundef %a, <2 x i32> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i32> %b, i32 %a, i32 1
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// CHECK: ret <2 x i32> [[VSET_LANE]]
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int32x2_t test_vset_lane_s32(int32_t a, int32x2_t b) {
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return vset_lane_s32(a, b, 1);
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}
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// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_p8(i8 noundef %a, <8 x i8> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7
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// CHECK: ret <8 x i8> [[VSET_LANE]]
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poly8x8_t test_vset_lane_p8(poly8_t a, poly8x8_t b) {
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return vset_lane_p8(a, b, 7);
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}
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// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_p16(i16 noundef %a, <4 x i16> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> %b, i16 %a, i32 3
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// CHECK: ret <4 x i16> [[VSET_LANE]]
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poly16x4_t test_vset_lane_p16(poly16_t a, poly16x4_t b) {
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return vset_lane_p16(a, b, 3);
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}
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// CHECK-LABEL: define{{.*}} <2 x float> @test_vset_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x float> %b, float %a, i32 1
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// CHECK: ret <2 x float> [[VSET_LANE]]
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float32x2_t test_vset_lane_f32(float32_t a, float32x2_t b) {
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return vset_lane_f32(a, b, 1);
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}
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// CHECK-LABEL: define{{.*}} <4 x half> @test_vset_lane_f16(ptr noundef %a, <4 x half> noundef %b) #0 {
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// CHECK: [[__REINT_246:%.*]] = alloca half, align 2
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// CHECK: [[__REINT1_246:%.*]] = alloca <4 x half>, align 8
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// CHECK: [[__REINT2_246:%.*]] = alloca <4 x i16>, align 8
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// CHECK: [[TMP0:%.*]] = load half, ptr %a, align 2
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// CHECK: store half [[TMP0]], ptr [[__REINT_246]], align 2
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// CHECK: store <4 x half> %b, ptr [[__REINT1_246]], align 8
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// CHECK: [[TMP2:%.*]] = load i16, ptr [[__REINT_246]], align 2
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// CHECK: [[TMP4:%.*]] = load <4 x i16>, ptr [[__REINT1_246]], align 8
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// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> [[TMP4]], i16 [[TMP2]], i32 3
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// CHECK: store <4 x i16> [[VSET_LANE]], ptr [[__REINT2_246]], align 8
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// CHECK: [[TMP8:%.*]] = load <4 x half>, ptr [[__REINT2_246]], align 8
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// CHECK: ret <4 x half> [[TMP8]]
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float16x4_t test_vset_lane_f16(float16_t *a, float16x4_t b) {
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return vset_lane_f16(*a, b, 3);
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}
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// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_u8(i8 noundef %a, <16 x i8> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15
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// CHECK: ret <16 x i8> [[VSET_LANE]]
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uint8x16_t test_vsetq_lane_u8(uint8_t a, uint8x16_t b) {
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return vsetq_lane_u8(a, b, 15);
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}
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// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_u16(i16 noundef %a, <8 x i16> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %b, i16 %a, i32 7
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// CHECK: ret <8 x i16> [[VSET_LANE]]
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uint16x8_t test_vsetq_lane_u16(uint16_t a, uint16x8_t b) {
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return vsetq_lane_u16(a, b, 7);
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}
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// CHECK-LABEL: define{{.*}} <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i32> %b, i32 %a, i32 3
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// CHECK: ret <4 x i32> [[VSET_LANE]]
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uint32x4_t test_vsetq_lane_u32(uint32_t a, uint32x4_t b) {
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return vsetq_lane_u32(a, b, 3);
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}
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// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_s8(i8 noundef %a, <16 x i8> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15
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// CHECK: ret <16 x i8> [[VSET_LANE]]
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int8x16_t test_vsetq_lane_s8(int8_t a, int8x16_t b) {
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return vsetq_lane_s8(a, b, 15);
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}
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// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_s16(i16 noundef %a, <8 x i16> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %b, i16 %a, i32 7
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// CHECK: ret <8 x i16> [[VSET_LANE]]
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int16x8_t test_vsetq_lane_s16(int16_t a, int16x8_t b) {
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return vsetq_lane_s16(a, b, 7);
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}
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// CHECK-LABEL: define{{.*}} <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i32> %b, i32 %a, i32 3
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// CHECK: ret <4 x i32> [[VSET_LANE]]
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int32x4_t test_vsetq_lane_s32(int32_t a, int32x4_t b) {
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return vsetq_lane_s32(a, b, 3);
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}
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// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_p8(i8 noundef %a, <16 x i8> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15
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// CHECK: ret <16 x i8> [[VSET_LANE]]
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poly8x16_t test_vsetq_lane_p8(poly8_t a, poly8x16_t b) {
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return vsetq_lane_p8(a, b, 15);
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}
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// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_p16(i16 noundef %a, <8 x i16> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %b, i16 %a, i32 7
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// CHECK: ret <8 x i16> [[VSET_LANE]]
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poly16x8_t test_vsetq_lane_p16(poly16_t a, poly16x8_t b) {
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return vsetq_lane_p16(a, b, 7);
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}
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// CHECK-LABEL: define{{.*}} <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x float> %b, float %a, i32 3
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// CHECK: ret <4 x float> [[VSET_LANE]]
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float32x4_t test_vsetq_lane_f32(float32_t a, float32x4_t b) {
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return vsetq_lane_f32(a, b, 3);
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}
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// CHECK-LABEL: define{{.*}} <8 x half> @test_vsetq_lane_f16(ptr noundef %a, <8 x half> noundef %b) #0 {
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// CHECK: [[__REINT_248:%.*]] = alloca half, align 2
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// CHECK: [[__REINT1_248:%.*]] = alloca <8 x half>, align 16
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// CHECK: [[__REINT2_248:%.*]] = alloca <8 x i16>, align 16
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// CHECK: [[TMP0:%.*]] = load half, ptr %a, align 2
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// CHECK: store half [[TMP0]], ptr [[__REINT_248]], align 2
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// CHECK: store <8 x half> %b, ptr [[__REINT1_248]], align 16
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// CHECK: [[TMP2:%.*]] = load i16, ptr [[__REINT_248]], align 2
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// CHECK: [[TMP4:%.*]] = load <8 x i16>, ptr [[__REINT1_248]], align 16
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// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> [[TMP4]], i16 [[TMP2]], i32 7
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// CHECK: store <8 x i16> [[VSET_LANE]], ptr [[__REINT2_248]], align 16
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// CHECK: [[TMP8:%.*]] = load <8 x half>, ptr [[__REINT2_248]], align 16
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// CHECK: ret <8 x half> [[TMP8]]
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float16x8_t test_vsetq_lane_f16(float16_t *a, float16x8_t b) {
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return vsetq_lane_f16(*a, b, 7);
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}
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// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_s64(i64 noundef %a, <1 x i64> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> %b, i64 %a, i32 0
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// CHECK: ret <1 x i64> [[VSET_LANE]]
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int64x1_t test_vset_lane_s64(int64_t a, int64x1_t b) {
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return vset_lane_s64(a, b, 0);
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}
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// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_u64(i64 noundef %a, <1 x i64> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> %b, i64 %a, i32 0
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// CHECK: ret <1 x i64> [[VSET_LANE]]
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uint64x1_t test_vset_lane_u64(uint64_t a, uint64x1_t b) {
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return vset_lane_u64(a, b, 0);
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}
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// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %b, i64 %a, i32 1
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// CHECK: ret <2 x i64> [[VSET_LANE]]
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int64x2_t test_vsetq_lane_s64(int64_t a, int64x2_t b) {
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return vsetq_lane_s64(a, b, 1);
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}
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// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #0 {
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// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %b, i64 %a, i32 1
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// CHECK: ret <2 x i64> [[VSET_LANE]]
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uint64x2_t test_vsetq_lane_u64(uint64_t a, uint64x2_t b) {
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return vsetq_lane_u64(a, b, 1);
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}
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