derek.holloway
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58 lines
3.2 KiB
C
58 lines
3.2 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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// RUN: %clang_cc1 -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm %s -o - \
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// RUN: | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK-RV64
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// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_veyron_v1(
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// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
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// CHECK-RV64-NEXT: [[ENTRY:.*:]]
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1567
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// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
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// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372036854710272
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// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
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// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
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// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 273
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// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
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// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i32
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// CHECK-RV64-NEXT: ret i32 [[CONV]]
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//
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int test_cpu_is_veyron_v1() {
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return __builtin_cpu_is("veyron-v1");
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}
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// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_spacemit_x60(
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// CHECK-RV64-SAME: ) #[[ATTR0]] {
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// CHECK-RV64-NEXT: [[ENTRY:.*:]]
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1808
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// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
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// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372035378380799
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// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
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// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
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// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1152921505839391232
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// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
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// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i32
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// CHECK-RV64-NEXT: ret i32 [[CONV]]
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//
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int test_cpu_is_spacemit_x60() {
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return __builtin_cpu_is("spacemit-x60");
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}
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// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_sifive_p550(
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// CHECK-RV64-SAME: ) #[[ATTR0]] {
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// CHECK-RV64-NEXT: [[ENTRY:.*:]]
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1161
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// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
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// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372036854775800
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// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
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// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
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// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 102892581
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// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
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// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i32
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// CHECK-RV64-NEXT: ret i32 [[CONV]]
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//
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int test_cpu_is_sifive_p550() {
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return __builtin_cpu_is("sifive-p550");
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}
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