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TheRock/compiler/amd-llvm/llvm/test/Analysis/DependenceAnalysis/PR188098.ll
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derek.holloway 7502bf64a4
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

67 lines
2.1 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -disable-output "-passes=print<da>" 2>&1 | FileCheck %s
; if (cond) {
; for (i = 0; i < 10; i++) {
; for (j = 0; j < 100; j++) {
; arg[j] = 0.0;
; }
; }
; } else {
; for (i = 0; i < 10; i++) {
; for (j = 0; j < 100; j++) {
; double x = arg[j];
; }
; }
; }
;
define void @fun(ptr %arg, i1 %cond) {
; CHECK-LABEL: 'fun'
; CHECK-NEXT: Src: store double 0.000000e+00, ptr %gep.0, align 8 --> Dst: store double 0.000000e+00, ptr %gep.0, align 8
; CHECK-NEXT: da analyze - output [* *]!
; CHECK-NEXT: Src: store double 0.000000e+00, ptr %gep.0, align 8 --> Dst: %i16 = load double, ptr %gep.1, align 8
; CHECK-NEXT: da analyze - flow [|<]!
; CHECK-NEXT: Src: %i16 = load double, ptr %gep.1, align 8 --> Dst: %i16 = load double, ptr %gep.1, align 8
; CHECK-NEXT: da analyze - input [* *]!
;
entry:
br i1 %cond, label %outer.0.header, label %outer.1.header
outer.0.header:
%i.0 = phi i64 [ %i.0.inc, %outer.0.latch ], [ 0, %entry ]
br label %inner.0
inner.0:
%j.0 = phi i64 [ %i.0, %outer.0.header ], [ %j.0.inc, %inner.0 ]
%j.0.inc = add i64 %j.0, 1
%gep.0 = getelementptr inbounds double, ptr %arg, i64 %j.0.inc
store double 0.000000e+00, ptr %gep.0
%ec.inner.0 = icmp eq i64 %j.0, 100
br i1 %ec.inner.0, label %outer.0.latch, label %inner.0
outer.0.latch:
%i.0.inc = add i64 %i.0, 1
%ec.outer.0 = icmp eq i64 %i.0.inc, 10
br i1 %ec.outer.0, label %exit, label %outer.0.header
outer.1.header:
%i.1 = phi i64 [ %i.1.inc, %outer.1.latch ], [ 0, %entry ]
br label %inner.1
inner.1:
%j.1 = phi i64 [ %i.1, %outer.1.header ], [ %j.1.inc, %inner.1 ]
%j.1.inc = add i64 %j.1, 1
%gep.1 = getelementptr inbounds double, ptr %arg, i64 %j.1.inc
%i16 = load double, ptr %gep.1
%ec.inner.1 = icmp eq i64 %j.1, 100
br i1 %ec.inner.1, label %outer.1.latch, label %inner.1
outer.1.latch:
%i.1.inc = add i64 %i.1, 1
%iec.outer.1 = icmp eq i64 %i.1.inc, 10
br i1 %iec.outer.1, label %exit, label %outer.1.header
exit:
ret void
}