derek.holloway
7502bf64a4
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477 lines
13 KiB
YAML
477 lines
13 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=regbankselect,instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# GPR variants should not use INSERT_SUBREG. FPR variants (DUP<ty>lane) should.
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...
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---
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name: DUPv4i32gpr
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv4i32gpr
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: %dup:fpr128 = DUPv4i32gpr %copy
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; CHECK-NEXT: $q0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%copy:gpr(i32) = COPY $w0
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%dup:fpr(<4 x i32>) = G_DUP %copy(i32)
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$q0 = COPY %dup(<4 x i32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv2i64gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: DUPv2i64gpr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr64 = COPY $x0
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; CHECK-NEXT: %dup:fpr128 = DUPv2i64gpr %copy
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; CHECK-NEXT: $q0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%copy:gpr(i64) = COPY $x0
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%dup:fpr(<2 x i64>) = G_DUP %copy(i64)
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$q0 = COPY %dup(<2 x i64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv2i32gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv2i32gpr
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: %dup:fpr64 = DUPv2i32gpr %copy
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; CHECK-NEXT: $d0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%copy:gpr(i32) = COPY $w0
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%dup:fpr(<2 x i32>) = G_DUP %copy(i32)
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$d0 = COPY %dup(<2 x i32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: DUPv4i32lane
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $s0
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; CHECK-LABEL: name: DUPv4i32lane
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; CHECK: liveins: $s0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:fpr32 = COPY $s0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub
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; CHECK-NEXT: %dup:fpr128 = DUPv4i32lane [[INSERT_SUBREG]], 0
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; CHECK-NEXT: $q0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%copy:fpr(i32) = COPY $s0
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%dup:fpr(<4 x i32>) = G_DUP %copy(i32)
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$q0 = COPY %dup(<4 x i32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv2i64lane
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $d0
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; CHECK-LABEL: name: DUPv2i64lane
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; CHECK: liveins: $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:fpr64 = COPY $d0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.dsub
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; CHECK-NEXT: %dup:fpr128 = DUPv2i64lane [[INSERT_SUBREG]], 0
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; CHECK-NEXT: $q0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%copy:fpr(i64) = COPY $d0
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%dup:fpr(<2 x i64>) = G_DUP %copy(i64)
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$q0 = COPY %dup(<2 x i64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv2i32lane
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $s0
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; CHECK-LABEL: name: DUPv2i32lane
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; CHECK: liveins: $s0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:fpr32 = COPY $s0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.ssub
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; CHECK-NEXT: %dup:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0
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; CHECK-NEXT: $d0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%copy:fpr(i32) = COPY $s0
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%dup:fpr(<2 x i32>) = G_DUP %copy(i32)
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$d0 = COPY %dup(<2 x i32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: DUPv4i16lane
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $h0
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; CHECK-LABEL: name: DUPv4i16lane
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; CHECK: liveins: $h0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:fpr16 = COPY $h0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub
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; CHECK-NEXT: %dup:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0
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; CHECK-NEXT: $d0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%copy:fpr(i16) = COPY $h0
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%dup:fpr(<4 x i16>) = G_DUP %copy(i16)
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$d0 = COPY %dup(<4 x i16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: DUPv4i16gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv4i16gpr
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: %dup:fpr64 = DUPv4i16gpr %copy
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; CHECK-NEXT: $d0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%copy:gpr(i32) = COPY $w0
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%dup:fpr(<4 x i16>) = G_DUP %copy(i32)
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$d0 = COPY %dup(<4 x i16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: DUPv8i16lane
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $h0
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; CHECK-LABEL: name: DUPv8i16lane
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; CHECK: liveins: $h0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:fpr16 = COPY $h0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %copy, %subreg.hsub
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; CHECK-NEXT: %dup:fpr128 = DUPv8i16lane [[INSERT_SUBREG]], 0
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; CHECK-NEXT: $q0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%copy:fpr(i16) = COPY $h0
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%dup:fpr(<8 x i16>) = G_DUP %copy(i16)
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$q0 = COPY %dup(<8 x i16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv8i16gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv8i16gpr
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: %dup:fpr128 = DUPv8i16gpr %copy
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; CHECK-NEXT: $q0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%copy:gpr(i32) = COPY $w0
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%dup:fpr(<8 x i16>) = G_DUP %copy(i32)
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$q0 = COPY %dup(<8 x i16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv8i16gpr_s16_src
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv8i16gpr_s16_src
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: %dup:fpr128 = DUPv8i16gpr %copy
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; CHECK-NEXT: $q0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%copy:gpr(i32) = COPY $w0
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%trunc:gpr(i16) = G_TRUNC %copy
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%dup:fpr(<8 x i16>) = G_DUP %trunc(i16)
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$q0 = COPY %dup(<8 x i16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv4s16gpr_s16_src
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv4s16gpr_s16_src
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: %dup:fpr64 = DUPv4i16gpr %copy
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; CHECK-NEXT: $d0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%copy:gpr(i32) = COPY $w0
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%trunc:gpr(i16) = G_TRUNC %copy
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%dup:fpr(<4 x i16>) = G_DUP %trunc(i16)
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$d0 = COPY %dup(<4 x i16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: DUPv8i8gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv8i8gpr
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: %dup:fpr64 = DUPv8i8gpr %copy
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; CHECK-NEXT: $d0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%copy:gpr(i32) = COPY $w0
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%dup:fpr(<8 x i8>) = G_DUP %copy(i32)
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$d0 = COPY %dup(<8 x i8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: DUPv8i8gpr_s8_src
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv8i8gpr_s8_src
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: %dup:fpr64 = DUPv8i8gpr %copy
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; CHECK-NEXT: $d0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%copy:gpr(i32) = COPY $w0
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%trunc:gpr(i8) = G_TRUNC %copy(i32)
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%dup:fpr(<8 x i8>) = G_DUP %trunc(i8)
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$d0 = COPY %dup(<8 x i8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: DUPv16i8gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv16i8gpr
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: %dup:fpr128 = DUPv16i8gpr %copy
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; CHECK-NEXT: $q0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%copy:gpr(i32) = COPY $w0
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%dup:fpr(<16 x i8>) = G_DUP %copy(i32)
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$q0 = COPY %dup(<16 x i8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: DUPv16i8gpr_s8_src
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: DUPv16i8gpr_s8_src
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: %dup:fpr128 = DUPv16i8gpr %copy
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; CHECK-NEXT: $q0 = COPY %dup
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%copy:gpr(i32) = COPY $w0
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%trunc:gpr(i8) = G_TRUNC %copy
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%dup:fpr(<16 x i8>) = G_DUP %trunc(i8)
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$q0 = COPY %dup(<16 x i8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: dup_v2p0
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: dup_v2p0
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
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; CHECK-NEXT: [[DUPv2i64gpr:%[0-9]+]]:fpr128 = DUPv2i64gpr [[COPY1]]
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; CHECK-NEXT: $q0 = COPY [[DUPv2i64gpr]]
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:gpr(p0) = COPY $x0
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%4:fpr(<2 x p0>) = G_DUP %0(p0)
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$q0 = COPY %4(<2 x p0>)
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RET_ReallyLR implicit $q0
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|
...
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---
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name: cst_v4s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0
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; CHECK-LABEL: name: cst_v4s32
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %dup:fpr128 = MOVIv4i32 3, 0
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|
; CHECK-NEXT: $q0 = COPY %dup
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%cst:gpr(i32) = G_CONSTANT i32 3
|
|
%dup:fpr(<4 x i32>) = G_DUP %cst(i32)
|
|
$q0 = COPY %dup(<4 x i32>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: cst_v8s8
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $w0
|
|
; CHECK-LABEL: name: cst_v8s8
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %dup:fpr64 = MOVIv8b_ns 3
|
|
; CHECK-NEXT: $d0 = COPY %dup
|
|
; CHECK-NEXT: RET_ReallyLR implicit $d0
|
|
%cst:gpr(i8) = G_CONSTANT i8 3
|
|
%dup:fpr(<8 x i8>) = G_DUP %cst(i8)
|
|
$d0 = COPY %dup(<8 x i8>)
|
|
RET_ReallyLR implicit $d0
|
|
...
|
|
---
|
|
name: cst_v2p0
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins: $w0
|
|
; CHECK-LABEL: name: cst_v2p0
|
|
; CHECK: liveins: $w0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
|
|
; CHECK-NEXT: %cst:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY %cst
|
|
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
|
|
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
|
|
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%cst:gpr(p0) = G_CONSTANT i64 3
|
|
%dup:fpr(<2 x p0>) = G_DUP %cst(p0)
|
|
$q0 = COPY %dup(<2 x p0>)
|
|
RET_ReallyLR implicit $q0
|
|
...
|
|
---
|
|
name: cstv4i16gpri32
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0.entry:
|
|
liveins:
|
|
; CHECK-LABEL: name: cstv4i16gpri32
|
|
; CHECK: %dup:fpr64 = MOVIv4i16 3, 0
|
|
; CHECK-NEXT: $d0 = COPY %dup
|
|
; CHECK-NEXT: RET_ReallyLR implicit $d0
|
|
%cst:gpr(i32) = G_CONSTANT i32 3
|
|
%dup:fpr(<4 x i16>) = G_DUP %cst(i32)
|
|
$d0 = COPY %dup(<4 x i16>)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|