derek.holloway
7502bf64a4
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329 lines
10 KiB
YAML
329 lines
10 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -mattr=+fullfp16 -o - | FileCheck %s
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...
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---
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name: load_s8_s16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x0
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; CHECK-LABEL: name: load_s8_s16
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; CHECK: liveins: $d0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG %4, %subreg.bsub
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; CHECK-NEXT: $h0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $x0 = COPY %3
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 4
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%2:fpr(s16), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s8))
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$h0 = COPY %2(s16)
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$x0 = COPY %3(p0)
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RET_ReallyLR implicit $d0
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...
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---
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name: load_s8_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x0
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; CHECK-LABEL: name: load_s8_s32
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; CHECK: liveins: $d0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.bsub
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; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $x0 = COPY %3
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 4
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%2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s8))
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$s0 = COPY %2(s32)
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$x0 = COPY %3(p0)
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RET_ReallyLR implicit $d0
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...
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---
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name: load_s8_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x0
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; CHECK-LABEL: name: load_s8_s64
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; CHECK: liveins: $d0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.bsub
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; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $x0 = COPY %3
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 4
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%2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s8))
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$d0 = COPY %2(s64)
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$x0 = COPY %3(p0)
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RET_ReallyLR implicit $d0
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...
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---
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name: load_s16_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x0
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; CHECK-LABEL: name: load_s16_s32
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; CHECK: liveins: $d0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (s16))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.hsub
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; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $x0 = COPY %3
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 4
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%2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s16))
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$s0 = COPY %2(s32)
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$x0 = COPY %3(p0)
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RET_ReallyLR implicit $d0
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...
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---
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name: load_s16_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x0
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; CHECK-LABEL: name: load_s16_s64
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; CHECK: liveins: $d0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (s16))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.hsub
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; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $x0 = COPY %3
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 4
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%2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s16))
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$d0 = COPY %2(s64)
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$x0 = COPY %3(p0)
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RET_ReallyLR implicit $d0
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...
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---
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name: load_s32_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x0
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; CHECK-LABEL: name: load_s32_s64
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; CHECK: liveins: $d0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpost [[COPY]], 4 :: (load (s32))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.ssub
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; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $x0 = COPY %3
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 4
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%2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 0 :: (load (s32))
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$d0 = COPY %2(s64)
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$x0 = COPY %3(p0)
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RET_ReallyLR implicit $d0
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...
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---
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name: load_s8_s16_pre
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x0
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; CHECK-LABEL: name: load_s8_s16_pre
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; CHECK: liveins: $d0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG %4, %subreg.bsub
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; CHECK-NEXT: $h0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $x0 = COPY %3
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 4
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%2:fpr(s16), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s8))
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$h0 = COPY %2(s16)
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$x0 = COPY %3(p0)
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RET_ReallyLR implicit $d0
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...
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---
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name: load_s8_s32_pre
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x0
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; CHECK-LABEL: name: load_s8_s32_pre
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; CHECK: liveins: $d0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.bsub
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; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $x0 = COPY %3
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 4
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%2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s8))
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$s0 = COPY %2(s32)
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$x0 = COPY %3(p0)
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RET_ReallyLR implicit $d0
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...
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---
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name: load_s8_s64_pre
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x0
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; CHECK-LABEL: name: load_s8_s64_pre
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; CHECK: liveins: $d0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.bsub
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; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $x0 = COPY %3
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 4
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%2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s8))
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$d0 = COPY %2(s64)
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$x0 = COPY %3(p0)
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RET_ReallyLR implicit $d0
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...
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---
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name: load_s16_s32_pre
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x0
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; CHECK-LABEL: name: load_s16_s32_pre
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; CHECK: liveins: $d0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (s16))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.hsub
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; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $x0 = COPY %3
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 4
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%2:fpr(s32), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s16))
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$s0 = COPY %2(s32)
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$x0 = COPY %3(p0)
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RET_ReallyLR implicit $d0
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...
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---
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name: load_s16_s64_pre
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x0
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; CHECK-LABEL: name: load_s16_s64_pre
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; CHECK: liveins: $d0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (s16))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.hsub
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; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $x0 = COPY %3
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 4
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%2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s16))
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$d0 = COPY %2(s64)
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$x0 = COPY %3(p0)
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RET_ReallyLR implicit $d0
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...
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---
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name: load_s32_s64_pre
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0, $x0
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; CHECK-LABEL: name: load_s32_s64_pre
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; CHECK: liveins: $d0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpre [[COPY]], 4 :: (load (s32))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.ssub
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; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: $x0 = COPY %3
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 4
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%2:fpr(s64), %3:gpr(p0) = G_INDEXED_LOAD %0:gpr, %1:gpr, 1 :: (load (s32))
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$d0 = COPY %2(s64)
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$x0 = COPY %3(p0)
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RET_ReallyLR implicit $d0
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...
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