derek.holloway
7502bf64a4
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126 lines
2.7 KiB
LLVM
126 lines
2.7 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s
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; Test invalid shift values. This will fall-back to SDAG.
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; AND
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define zeroext i8 @and_rs_i8(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: and_rs_i8
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; CHECK: and [[REG:w[0-9]+]], w0, w8
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
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%1 = shl i8 %b, 8
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%2 = and i8 %a, %1
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ret i8 %2
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}
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define zeroext i16 @and_rs_i16(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: and_rs_i16
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; CHECK: and [[REG:w[0-9]+]], w0, w8
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
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%1 = shl i16 %b, 16
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%2 = and i16 %a, %1
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ret i16 %2
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}
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define i32 @and_rs_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: and_rs_i32
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; CHECK: and w0, w0, w8
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%1 = shl i32 %b, 32
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%2 = and i32 %a, %1
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ret i32 %2
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}
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define i64 @and_rs_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: and_rs_i64
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; CHECK: and x0, x0, x8
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%1 = shl i64 %b, 64
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%2 = and i64 %a, %1
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ret i64 %2
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}
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; OR
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define zeroext i8 @or_rs_i8(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: or_rs_i8
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; CHECK: orr [[REG:w[0-9]+]], w0, w8
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
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%1 = shl i8 %b, 8
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%2 = or i8 %a, %1
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ret i8 %2
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}
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define zeroext i16 @or_rs_i16(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: or_rs_i16
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; CHECK: orr [[REG:w[0-9]+]], w0, w8
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
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%1 = shl i16 %b, 16
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%2 = or i16 %a, %1
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ret i16 %2
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}
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define i32 @or_rs_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: or_rs_i32
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; CHECK: orr w0, w0, w8
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%1 = shl i32 %b, 32
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%2 = or i32 %a, %1
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ret i32 %2
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}
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define i64 @or_rs_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: or_rs_i64
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; CHECK: orr x0, x0, x8
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%1 = shl i64 %b, 64
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%2 = or i64 %a, %1
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ret i64 %2
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}
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; XOR
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define zeroext i8 @xor_rs_i8(i8 %a, i8 %b) {
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; CHECK-LABEL: xor_rs_i8
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; CHECK: eor [[REG:w[0-9]+]], w0, w8
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff
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%1 = shl i8 %b, 8
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%2 = xor i8 %a, %1
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ret i8 %2
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}
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define zeroext i16 @xor_rs_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: xor_rs_i16
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; CHECK: eor [[REG:w[0-9]+]], w0, w8
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; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff
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%1 = shl i16 %b, 16
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%2 = xor i16 %a, %1
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ret i16 %2
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}
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define i32 @xor_rs_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: xor_rs_i32
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; CHECK: eor w0, w0, w8
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%1 = shl i32 %b, 32
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%2 = xor i32 %a, %1
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ret i32 %2
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}
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define i64 @xor_rs_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: xor_rs_i64
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; CHECK: eor x0, x0, x8
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%1 = shl i64 %b, 64
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%2 = xor i64 %a, %1
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ret i64 %2
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}
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;ADD
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define i32 @add_rs_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: add_rs_i32
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; CHECK: add w0, w0, w8
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%1 = shl i32 %b, 32
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%2 = add i32 %a, %1
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ret i32 %2
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}
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define i64 @add_rs_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: add_rs_i64
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; CHECK: add x0, x0, x8
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%1 = shl i64 %b, 64
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%2 = add i64 %a, %1
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ret i64 %2
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}
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