derek.holloway
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127 lines
5.8 KiB
LLVM
127 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
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; Ensure we use the CC result of SVE compare instructions when branching.
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define void @sve_cmplt_setcc(ptr %out, <vscale x 8 x i16> %in, <vscale x 8 x i1> %pg) {
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; CHECK-LABEL: sve_cmplt_setcc:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmplt p1.h, p0/z, z0.h, #0
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; CHECK-NEXT: b.eq .LBB0_2
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; CHECK-NEXT: // %bb.1: // %if.then
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; CHECK-NEXT: st1h { z0.h }, p0, [x0]
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; CHECK-NEXT: .LBB0_2: // %if.end
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; CHECK-NEXT: ret
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entry:
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%0 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %in, <vscale x 2 x i64> zeroinitializer)
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%1 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %0)
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br i1 %1, label %if.then, label %if.end
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if.then:
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tail call void @llvm.masked.store.nxv8i16.p0(<vscale x 8 x i16> %in, ptr %out, i32 2, <vscale x 8 x i1> %pg)
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br label %if.end
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if.end:
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ret void
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}
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; Ensure we use the inverted CC result of SVE compare instructions when branching.
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define void @sve_cmplt_setcc_inverted(ptr %out, <vscale x 8 x i16> %in, <vscale x 8 x i1> %pg) {
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; CHECK-LABEL: sve_cmplt_setcc_inverted:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmplt p1.h, p0/z, z0.h, #0
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; CHECK-NEXT: b.ne .LBB1_2
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; CHECK-NEXT: // %bb.1: // %if.then
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; CHECK-NEXT: st1h { z0.h }, p0, [x0]
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; CHECK-NEXT: .LBB1_2: // %if.end
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; CHECK-NEXT: ret
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entry:
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%0 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %in, <vscale x 2 x i64> zeroinitializer)
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%1 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %0)
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br i1 %1, label %if.end, label %if.then
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if.then:
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tail call void @llvm.masked.store.nxv8i16.p0(<vscale x 8 x i16> %in, ptr %out, i32 2, <vscale x 8 x i1> %pg)
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br label %if.end
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if.end:
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ret void
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}
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; Ensure we combine setcc and csel so as to not end up with an extra compare
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define void @sve_cmplt_setcc_hslo(ptr %out, <vscale x 8 x i16> %in, <vscale x 8 x i1> %pg) {
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; CHECK-LABEL: sve_cmplt_setcc_hslo:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p1.h
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; CHECK-NEXT: cmplt p2.h, p0/z, z0.h, #0
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; CHECK-NEXT: and p1.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: ptest p1, p2.b
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; CHECK-NEXT: b.hs .LBB2_2
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; CHECK-NEXT: // %bb.1: // %if.then
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; CHECK-NEXT: st1h { z0.h }, p0, [x0]
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; CHECK-NEXT: .LBB2_2: // %if.end
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; CHECK-NEXT: ret
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entry:
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%0 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %in, <vscale x 2 x i64> zeroinitializer)
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%1 = tail call i1 @llvm.aarch64.sve.ptest.last.nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %0)
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br i1 %1, label %if.then, label %if.end
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if.then:
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tail call void @llvm.masked.store.nxv8i16.p0(<vscale x 8 x i16> %in, ptr %out, i32 2, <vscale x 8 x i1> %pg)
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br label %if.end
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if.end:
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ret void
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}
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; Fold away the redundant setcc::
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; setcc(ne, <all ones>, sext(nxvNi1 ...), splat(0))
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; -> nxvNi1 ...
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define <vscale x 16 x i1> @sve_cmpne_setcc_all_true_sext(<vscale x 16 x i8> %vec, <vscale x 16 x i1> %pg) {
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; CHECK-LABEL: sve_cmpne_setcc_all_true_sext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%alltrue.ins = insertelement <vscale x 16 x i1> poison, i1 true, i32 0
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%alltrue = shufflevector <vscale x 16 x i1> %alltrue.ins, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
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%pg.sext = sext <vscale x 16 x i1> %pg to <vscale x 16 x i8>
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%cmp2 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %alltrue, <vscale x 16 x i8> %pg.sext, <vscale x 16 x i8> zeroinitializer)
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ret <vscale x 16 x i1> %cmp2
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}
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; Fold away the redundant setcc::
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; setcc(ne, pred, sext(setcc(ne, pred, ..., splat(0))), splat(0))
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; -> setcc(ne, pred, ..., splat(0))
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define <vscale x 16 x i1> @sve_cmpne_setcc_equal_pred(<vscale x 16 x i8> %vec, <vscale x 16 x i1> %pg) {
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; CHECK-LABEL: sve_cmpne_setcc_equal_pred:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, #0
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; CHECK-NEXT: ret
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%cmp1 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %vec, <vscale x 16 x i8> zeroinitializer)
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%cmp1.sext = sext <vscale x 16 x i1> %cmp1 to <vscale x 16 x i8>
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%cmp2 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %cmp1.sext, <vscale x 16 x i8> zeroinitializer)
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ret <vscale x 16 x i1> %cmp2
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}
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; Combine:
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; setcc(ne, pred1, sext(setcc(ne, pred2, ..., splat(0))), splat(0))
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; -> setcc(ne, and(pred1, pred2), ..., splat(0))
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define <vscale x 16 x i1> @sve_cmpne_setcc_different_pred(<vscale x 16 x i8> %vec, <vscale x 16 x i1> %pg1, <vscale x 16 x i1> %pg2) {
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; CHECK-LABEL: sve_cmpne_setcc_different_pred:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmpne p2.b, p0/z, z0.b, #0
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; CHECK-NEXT: and p0.b, p2/z, p2.b, p1.b
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; CHECK-NEXT: ret
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%cmp1 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %pg1, <vscale x 16 x i8> %vec, <vscale x 16 x i8> zeroinitializer)
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%cmp1.sext = sext <vscale x 16 x i1> %cmp1 to <vscale x 16 x i8>
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%cmp2 = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> %pg2, <vscale x 16 x i8> %cmp1.sext, <vscale x 16 x i8> zeroinitializer)
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ret <vscale x 16 x i1> %cmp2
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}
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declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
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declare i1 @llvm.aarch64.sve.ptest.any.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
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declare i1 @llvm.aarch64.sve.ptest.last.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.cmplt.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
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declare void @llvm.masked.store.nxv8i16.p0(<vscale x 8 x i16>, ptr, i32, <vscale x 8 x i1>)
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