derek/TheRock
1
0 Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
1a182e2dac58879f215c0fad0f5f78c76dcafe56
TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
T
derek.holloway 7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
Details
CodeQL / Analyze (python) (push) Canceled after 0s
Details
pre-commit / pre-commit (push) Canceled after 0s
Details
Multi-Arch CI / setup (push) Canceled after 0s
Details
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Details
Setup (Multi-Arch) / setup (push) Canceled after 0s
Details
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Details
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
Details
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Details
Multi-Arch CI / CI Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Details
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
Details
Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

369 lines
9.4 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -enable-subreg-liveness -mattr=+sve -force-streaming-compatible < %s | FileCheck %s
; RUN: llc -enable-subreg-liveness -mattr=+sme -force-streaming < %s | FileCheck %s
; RUN: llc -enable-subreg-liveness -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
target triple = "aarch64-unknown-linux-gnu"
define <4 x i8> @load_v4i8(ptr %a) {
; CHECK-LABEL: load_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl4
; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: ldrb w8, [x0, #3]
; NONEON-NOSVE-NEXT: strh w8, [sp, #14]
; NONEON-NOSVE-NEXT: ldrb w8, [x0, #2]
; NONEON-NOSVE-NEXT: strh w8, [sp, #12]
; NONEON-NOSVE-NEXT: ldrb w8, [x0, #1]
; NONEON-NOSVE-NEXT: strh w8, [sp, #10]
; NONEON-NOSVE-NEXT: ldrb w8, [x0]
; NONEON-NOSVE-NEXT: strh w8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%load = load <4 x i8>, ptr %a
ret <4 x i8> %load
}
define <8 x i8> @load_v8i8(ptr %a) {
; CHECK-LABEL: load_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v8i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <8 x i8>, ptr %a
ret <8 x i8> %load
}
define <16 x i8> @load_v16i8(ptr %a) {
; CHECK-LABEL: load_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v16i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <16 x i8>, ptr %a
ret <16 x i8> %load
}
define <32 x i8> @load_v32i8(ptr %a) {
; CHECK-LABEL: load_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v32i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <32 x i8>, ptr %a
ret <32 x i8> %load
}
define <2 x i16> @load_v2i16(ptr %a) {
; CHECK-LABEL: load_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl2
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v2i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: ldrh w8, [x0, #2]
; NONEON-NOSVE-NEXT: str w8, [sp, #12]
; NONEON-NOSVE-NEXT: ldrh w8, [x0]
; NONEON-NOSVE-NEXT: str w8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%load = load <2 x i16>, ptr %a
ret <2 x i16> %load
}
define <2 x half> @load_v2f16(ptr %a) {
; CHECK-LABEL: load_v2f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr s0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v2f16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #16
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT: ldr w8, [x0]
; NONEON-NOSVE-NEXT: str w8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%load = load <2 x half>, ptr %a
ret <2 x half> %load
}
define <4 x i16> @load_v4i16(ptr %a) {
; CHECK-LABEL: load_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <4 x i16>, ptr %a
ret <4 x i16> %load
}
define <4 x half> @load_v4f16(ptr %a) {
; CHECK-LABEL: load_v4f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4f16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <4 x half>, ptr %a
ret <4 x half> %load
}
define <8 x i16> @load_v8i16(ptr %a) {
; CHECK-LABEL: load_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v8i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <8 x i16>, ptr %a
ret <8 x i16> %load
}
define <8 x half> @load_v8f16(ptr %a) {
; CHECK-LABEL: load_v8f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v8f16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <8 x half>, ptr %a
ret <8 x half> %load
}
define <16 x i16> @load_v16i16(ptr %a) {
; CHECK-LABEL: load_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v16i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <16 x i16>, ptr %a
ret <16 x i16> %load
}
define <16 x half> @load_v16f16(ptr %a) {
; CHECK-LABEL: load_v16f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v16f16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <16 x half>, ptr %a
ret <16 x half> %load
}
define <2 x i32> @load_v2i32(ptr %a) {
; CHECK-LABEL: load_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v2i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <2 x i32>, ptr %a
ret <2 x i32> %load
}
define <2 x float> @load_v2f32(ptr %a) {
; CHECK-LABEL: load_v2f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v2f32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <2 x float>, ptr %a
ret <2 x float> %load
}
define <4 x i32> @load_v4i32(ptr %a) {
; CHECK-LABEL: load_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <4 x i32>, ptr %a
ret <4 x i32> %load
}
define <4 x float> @load_v4f32(ptr %a) {
; CHECK-LABEL: load_v4f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4f32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <4 x float>, ptr %a
ret <4 x float> %load
}
define <8 x i32> @load_v8i32(ptr %a) {
; CHECK-LABEL: load_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <8 x i32>, ptr %a
ret <8 x i32> %load
}
define <8 x float> @load_v8f32(ptr %a) {
; CHECK-LABEL: load_v8f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v8f32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <8 x float>, ptr %a
ret <8 x float> %load
}
define <1 x i64> @load_v1i64(ptr %a) {
; CHECK-LABEL: load_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v1i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <1 x i64>, ptr %a
ret <1 x i64> %load
}
define <1 x double> @load_v1f64(ptr %a) {
; CHECK-LABEL: load_v1f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v1f64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <1 x double>, ptr %a
ret <1 x double> %load
}
define <2 x i64> @load_v2i64(ptr %a) {
; CHECK-LABEL: load_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <2 x i64>, ptr %a
ret <2 x i64> %load
}
define <2 x double> @load_v2f64(ptr %a) {
; CHECK-LABEL: load_v2f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v2f64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <2 x double>, ptr %a
ret <2 x double> %load
}
define <4 x i64> @load_v4i64(ptr %a) {
; CHECK-LABEL: load_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <4 x i64>, ptr %a
ret <4 x i64> %load
}
define <4 x double> @load_v4f64(ptr %a) {
; CHECK-LABEL: load_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4f64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <4 x double>, ptr %a
ret <4 x double> %load
}
Reference in new issue View Git Blame Copy Permalink