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78 lines
2.9 KiB
YAML
78 lines
2.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s
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# COM: Check that the pass doesn't crash.
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---
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name: test_inline_asm
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: true
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_inline_asm
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0", attdialect, regdef:VGPR_32, def %5(s32)
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[FMUL]], %5, [[COPY2]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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%2:vgpr(s32) = COPY %1(s32)
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%3:vgpr(s32) = G_FMUL %0, %2
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%4:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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INLINEASM &"v_mov_b32 $0, 0", attdialect, regdef:VGPR_32, def %5:vgpr_32
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%6:vgpr(s32) = COPY %4(s32)
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%7:vgpr(s32) = nnan G_AMDGPU_FMED3 %3(s32), %5(s32), %6(s32)
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$vgpr0 = COPY %7(s32)
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...
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---
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name: test_unmerge_values
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: true
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_unmerge_values
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
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; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_FMED3 [[FMUL]], [[C2]], [[COPY2]]
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; CHECK-NEXT: $vgpr0 = COPY [[C2]](s32)
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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%2:vgpr(s32) = COPY %1(s32)
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%3:vgpr(s32) = G_FMUL %0, %2
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%4:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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%5:vgpr(s64) = G_CONSTANT i64 123456789
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%6:vgpr(s32), %7:vgpr(s32) = G_UNMERGE_VALUES %5(s64)
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%8:vgpr(s32) = COPY %4(s32)
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%9:vgpr(s32) = nnan G_AMDGPU_FMED3 %3(s32), %7(s32), %8(s32)
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$vgpr0 = COPY %7(s32)
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...
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