derek.holloway
7502bf64a4
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328 lines
10 KiB
YAML
328 lines
10 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
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---
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name: and_s1_sgpr_sgpr
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: and_s1_sgpr_sgpr
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[COPY1]]
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; CHECK-NEXT: S_ENDPGM 0, implicit [[AND]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s1) = G_TRUNC %0
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%3:_(s1) = G_TRUNC %1
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%4:_(s1) = G_AND %2, %3
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%5:_(s32) = G_ANYEXT %4
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S_ENDPGM 0, implicit %5
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...
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---
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name: and_s1_scc_scc
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: and_s1_scc_scc
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
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; CHECK-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
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; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP]], [[ICMP1]]
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; CHECK-NEXT: S_ENDPGM 0, implicit [[AND]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s1) = G_ICMP intpred(eq), %0, %2
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%4:_(s1) = G_ICMP intpred(eq), %1, %2
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%5:_(s1) = G_AND %3, %4
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%6:_(s32) = G_ANYEXT %5
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S_ENDPGM 0, implicit %6
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...
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---
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name: and_s1_vgpr_vgpr
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: and_s1_vgpr_vgpr
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND1]](s32), [[C1]]
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; CHECK-NEXT: [[AND2:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[AND2]](s1), [[C]], [[C1]]
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s1) = G_TRUNC %0
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%3:_(s1) = G_TRUNC %1
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%4:_(s1) = G_AND %2, %3
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%5:_(s32) = G_ANYEXT %4
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...
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---
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name: and_s1_vcc_vcc
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: and_s1_vcc_vcc
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY2]]
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
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; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s1) = G_ICMP intpred(eq), %0, %2
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%4:_(s1) = G_ICMP intpred(eq), %1, %2
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%5:_(s1) = G_AND %3, %4
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...
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---
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name: and_s1_sgpr_vgpr
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: and_s1_sgpr_vgpr
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; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
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; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY]](s32)
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; CHECK-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[AMDGPU_COPY_VCC_SCC]], [[ICMP]]
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $vgpr0
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%2:_(s1) = G_TRUNC %0
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%3:_(s1) = G_TRUNC %1
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%4:_(s1) = G_AND %2, %3
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...
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---
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name: and_s1_vgpr_sgpr
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr0
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; CHECK-LABEL: name: and_s1_vgpr_sgpr
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; CHECK: liveins: $vgpr0, $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
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; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY1]](s32)
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; CHECK-NEXT: [[AND1:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[AMDGPU_COPY_VCC_SCC]]
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $sgpr0
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%2:_(s1) = G_TRUNC %0
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%3:_(s1) = G_TRUNC %1
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%4:_(s1) = G_AND %2, %3
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...
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# FIXME: Should just change the result bank of the scc compare.
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---
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name: and_s1_scc_vcc
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: and_s1_scc_vcc
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; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY2]]
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; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[ICMP]](s32)
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; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[AMDGPU_COPY_VCC_SCC]], [[ICMP1]]
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $vgpr0
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s1) = G_ICMP intpred(eq), %0, %2
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%4:_(s1) = G_ICMP intpred(eq), %1, %2
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%5:_(s1) = G_AND %3, %4
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...
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---
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name: and_s1_vcc_scc
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: and_s1_vcc_scc
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY2]]
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
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; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s1) = G_ICMP intpred(eq), %0, %2
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%4:_(s1) = G_ICMP intpred(eq), %1, %2
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%5:_(s1) = G_AND %3, %4
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...
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# Test with a known result bank
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# ---
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# name: and_s1_vcc_sgpr_sgpr
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# legalized: true
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# body: |
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# bb.0:
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# liveins: $sgpr0, $sgpr1
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# %0:_(s32) = COPY $sgpr0
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# %1:_(s32) = COPY $sgpr1
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# %2:_(s1) = G_TRUNC %0
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# %3:_(s1) = G_TRUNC %1
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# %4:vcc(s1) = G_AND %2, %3
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# ...
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# ---
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# name: and_s1_vcc_vgpr_vgpr
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# legalized: true
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# body: |
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# bb.0:
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# liveins: $vgpr0, $vgpr1
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# %0:_(s32) = COPY $vgpr0
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# %1:_(s32) = COPY $vgpr1
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# %2:_(s1) = G_TRUNC %0
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# %3:_(s1) = G_TRUNC %1
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# %4:vcc(s1) = G_AND %2, %3
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# ...
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# ---
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# name: and_s1_vcc_vgpr_sgpr
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# legalized: true
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# body: |
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# bb.0:
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# liveins: $vgpr0, $sgpr0
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# %0:_(s32) = COPY $vgpr0
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# %1:_(s32) = COPY $sgpr0
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# %2:_(s1) = G_TRUNC %0
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# %3:_(s1) = G_TRUNC %1
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# %4:vcc(s1) = G_AND %2, %3
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# ...
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# ---
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# name: and_s1_vcc_sgpr_vgpr
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# legalized: true
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# body: |
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# bb.0:
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# liveins: $vgpr0, $sgpr0
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# %0:_(s32) = COPY $sgpr0
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# %1:_(s32) = COPY $vgpr0
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# %2:_(s1) = G_TRUNC %0
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# %3:_(s1) = G_TRUNC %1
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# %4:vcc(s1) = G_AND %2, %3
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# ...
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---
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name: and_s1_vgpr_sgpr_sgpr
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: and_s1_vgpr_sgpr_sgpr
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY2]], [[C]]
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; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[AND1]](s32)
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; CHECK-NEXT: [[AND2:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[AMDGPU_COPY_VCC_SCC]]
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $vgpr0
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%3:_(s1) = G_TRUNC %0
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%4:_(s1) = G_TRUNC %1
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%5:_(s1) = G_TRUNC %2
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%6:_(s1) = G_AND %3, %4
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%7:_(s1) = G_AND %5, %6
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...
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---
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name: and_s1_sgpr_sgpr_sgpr
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: and_s1_sgpr_sgpr_sgpr
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[COPY2]], [[AND]]
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; CHECK-NEXT: S_ENDPGM 0, implicit [[AND1]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $sgpr0
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%3:_(s1) = G_TRUNC %0
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%4:_(s1) = G_TRUNC %1
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%5:_(s1) = G_TRUNC %2
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%6:_(s1) = G_AND %3, %4
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%7:_(s1) = G_AND %5, %6
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%8:_(s32) = G_ANYEXT %7
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S_ENDPGM 0, implicit %8
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...
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