derek.holloway
7502bf64a4
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140 lines
5.6 KiB
YAML
140 lines
5.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -run-pass=instruction-select -mattr=+real-true16 -o - %s | FileCheck -check-prefix=GFX11 %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -run-pass=instruction-select -mattr=+real-true16 -o - %s | FileCheck -check-prefix=GFX12 %s
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---
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name: test_merge_values_s16_into_s32_sgpr
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX11-LABEL: name: test_merge_values_s16_into_s32_sgpr
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; GFX11: liveins: $sgpr0, $sgpr1
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; GFX11-NEXT: {{ $}}
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; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX11-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
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; GFX11-NEXT: $sgpr0 = COPY [[S_PACK_LL_B32_B16_]]
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;
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; GFX12-LABEL: name: test_merge_values_s16_into_s32_sgpr
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; GFX12: liveins: $sgpr0, $sgpr1
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; GFX12-NEXT: {{ $}}
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; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX12-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
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; GFX12-NEXT: $sgpr0 = COPY [[S_PACK_LL_B32_B16_]]
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%0:sreg_32(s32) = COPY $sgpr0
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%1:sreg_32(s32) = COPY $sgpr1
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%2:sreg_32(s16) = G_TRUNC %0:sreg_32(s32)
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%3:sreg_32(s16) = G_TRUNC %1:sreg_32(s32)
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%4:sreg_32(s32) = G_MERGE_VALUES %2:sreg_32(s16), %3:sreg_32(s16)
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$sgpr0 = COPY %4:sreg_32(s32)
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...
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---
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name: test_build_vector_s16_into_s32_sgpr
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX11-LABEL: name: test_build_vector_s16_into_s32_sgpr
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; GFX11: liveins: $sgpr0, $sgpr1
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; GFX11-NEXT: {{ $}}
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; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX11-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
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; GFX11-NEXT: $sgpr0 = COPY [[S_PACK_LL_B32_B16_]]
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;
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; GFX12-LABEL: name: test_build_vector_s16_into_s32_sgpr
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; GFX12: liveins: $sgpr0, $sgpr1
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; GFX12-NEXT: {{ $}}
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; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX12-NEXT: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
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; GFX12-NEXT: $sgpr0 = COPY [[S_PACK_LL_B32_B16_]]
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%0:sreg_32(s32) = COPY $sgpr0
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%1:sreg_32(s32) = COPY $sgpr1
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%2:sreg_32(s16) = G_TRUNC %0:sreg_32(s32)
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%3:sreg_32(s16) = G_TRUNC %1:sreg_32(s32)
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%4:sreg_32(<2 x s16>) = G_BUILD_VECTOR %2:sreg_32(s16), %3:sreg_32(s16)
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$sgpr0 = COPY %4:sreg_32(<2 x s16>)
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...
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---
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name: test_merge_values_s16_into_s32_vgpr
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
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; GFX11-LABEL: name: test_merge_values_s16_into_s32_vgpr
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; GFX11: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
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; GFX11-NEXT: {{ $}}
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; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
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; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
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; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY2]], %subreg.lo16, [[COPY3]], %subreg.hi16
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; GFX11-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
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;
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; GFX12-LABEL: name: test_merge_values_s16_into_s32_vgpr
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; GFX12: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
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; GFX12-NEXT: {{ $}}
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; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
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; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
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; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY2]], %subreg.lo16, [[COPY3]], %subreg.hi16
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; GFX12-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
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%0:vgpr_32(s32) = COPY $vgpr0
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%1:vgpr_32(s32) = COPY $vgpr1
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%2:vgpr_16(s16) = G_TRUNC %0:vgpr_32(s32)
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%3:vgpr_16(s16) = G_TRUNC %1:vgpr_32(s32)
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%4:vgpr_32(s32) = G_MERGE_VALUES %2:vgpr_16(s16), %3:vgpr_16(s16)
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$vgpr0 = COPY %4:vgpr_32(s32)
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...
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---
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name: test_build_vector_s16_into_s32_vgpr
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX11-LABEL: name: test_build_vector_s16_into_s32_vgpr
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; GFX11: liveins: $vgpr0, $vgpr1
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; GFX11-NEXT: {{ $}}
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; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
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; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
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; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY2]], %subreg.lo16, [[COPY3]], %subreg.hi16
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; GFX11-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
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;
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; GFX12-LABEL: name: test_build_vector_s16_into_s32_vgpr
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; GFX12: liveins: $vgpr0, $vgpr1
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; GFX12-NEXT: {{ $}}
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; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
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; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
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; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY2]], %subreg.lo16, [[COPY3]], %subreg.hi16
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; GFX12-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
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%0:vgpr_32(s32) = COPY $vgpr0
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%1:vgpr_32(s32) = COPY $vgpr1
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%2:vgpr_16(s16) = G_TRUNC %0:vgpr_32(s32)
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%3:vgpr_16(s16) = G_TRUNC %1:vgpr_32(s32)
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%4:vgpr_32(<2 x s16>) = G_BUILD_VECTOR %2:vgpr_16(s16), %3:vgpr_16(s16)
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$vgpr0 = COPY %4:vgpr_32(<2 x s16>)
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...
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