derek.holloway
7502bf64a4
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139 lines
8.2 KiB
YAML
139 lines
8.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW64 %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=FLATSCRW32 %s
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# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=MUBUF %s
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---
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# S_CSELECT_B32 with a frame index true-operand, preceded immediately by
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# S_AND_B64 which produces SCC. The frame index has a non-zero offset so
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# the ADDC path applies. Verify ADDC+BITCMP1+BITSET0 is generated.
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name: s_cselect_b32_fi_after_scc_producer
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 64, alignment: 4 }
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- { id: 1, size: 4, alignment: 4 }
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr33'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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bb.0:
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liveins: $sgpr4, $sgpr5, $sgpr6
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; S_AND_B64 produces SCC. The regscavenger backward scan from S_CSELECT_B32
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; will call stepBackward on S_AND_B64, removing SCC from liveness. Without
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; the fix, RS->isRegUsed(SCC) returns false -> NeedSaveSCC=false -> plain
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; S_ADD_I32 is inserted before S_CSELECT_B32 -> SCC clobbered -> wrong result.
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; FLATSCRW64-LABEL: name: s_cselect_b32_fi_after_scc_producer
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; FLATSCRW64: liveins: $sgpr4, $sgpr5, $sgpr6
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; FLATSCRW64-NEXT: {{ $}}
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; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02
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; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
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; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
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; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5
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; FLATSCRW64-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 killed renamable $sgpr4_sgpr5, $exec, implicit-def $scc
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; FLATSCRW64-NEXT: $sgpr5 = S_ADDC_U32 $sgpr32, 64, implicit-def $scc, implicit $scc
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; FLATSCRW64-NEXT: S_BITCMP1_B32 $sgpr5, 0, implicit-def $scc
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; FLATSCRW64-NEXT: $sgpr5 = S_BITSET0_B32 0, $sgpr5
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; FLATSCRW64-NEXT: renamable $sgpr4 = S_CSELECT_B32 killed $sgpr5, $sgpr6, implicit $scc
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; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr4
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;
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; FLATSCRW32-LABEL: name: s_cselect_b32_fi_after_scc_producer
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; FLATSCRW32: liveins: $sgpr4, $sgpr5, $sgpr6
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; FLATSCRW32-NEXT: {{ $}}
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; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02
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; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
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; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
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; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5
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; FLATSCRW32-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 killed renamable $sgpr4_sgpr5, $exec, implicit-def $scc
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; FLATSCRW32-NEXT: $sgpr5 = S_ADDC_U32 $sgpr32, 64, implicit-def $scc, implicit $scc
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; FLATSCRW32-NEXT: S_BITCMP1_B32 $sgpr5, 0, implicit-def $scc
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; FLATSCRW32-NEXT: $sgpr5 = S_BITSET0_B32 0, $sgpr5
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; FLATSCRW32-NEXT: renamable $sgpr4 = S_CSELECT_B32 killed $sgpr5, $sgpr6, implicit $scc
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; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr4
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;
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; MUBUF-LABEL: name: s_cselect_b32_fi_after_scc_producer
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; MUBUF: liveins: $sgpr4, $sgpr5, $sgpr6
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; MUBUF-NEXT: {{ $}}
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; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6
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; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
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; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
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; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5
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; MUBUF-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 killed renamable $sgpr4_sgpr5, $exec, implicit-def $scc
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; MUBUF-NEXT: $sgpr5 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc
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; MUBUF-NEXT: $sgpr5 = S_ADD_I32 killed $sgpr5, 64, implicit-def $scc
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; MUBUF-NEXT: renamable $sgpr4 = S_CSELECT_B32 killed $sgpr5, $sgpr6, implicit $scc
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; MUBUF-NEXT: SI_RETURN implicit $sgpr4
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renamable $sgpr4_sgpr5 = S_AND_B64 killed renamable $sgpr4_sgpr5, $exec, implicit-def $scc
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; %stack.1 is at offset 64 from frame base (non-zero), so eliminateFrameIndex
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; cannot use the trivial FrameReg-only path. Verify it uses ADDC+BITCMP1+BITSET0.
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renamable $sgpr4 = S_CSELECT_B32 %stack.1, $sgpr6, implicit $scc
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SI_RETURN implicit $sgpr4
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...
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---
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# S_ADDC_U32 with a frame index source-operand, preceded by S_AND_B64 which
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# produces SCC. S_ADDC_U32 reads SCC, so frame index elimination must use the
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# ADDC+BITCMP1+BITSET0 sequence to preserve the incoming SCC value.
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name: s_addc_u32_fi_after_and_scc_producer
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 64, alignment: 4 }
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- { id: 1, size: 4, alignment: 4 }
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr33'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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bb.0:
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liveins: $sgpr4, $sgpr5, $sgpr6
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; S_AND_B64 produces SCC. S_ADDC_U32 has a frame index source operand and
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; reads SCC (implicit $scc), so frame index elimination must preserve SCC
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; using ADDC+BITCMP1+BITSET0 before expanding the frame index.
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; FLATSCRW64-LABEL: name: s_addc_u32_fi_after_and_scc_producer
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; FLATSCRW64: liveins: $sgpr4, $sgpr5, $sgpr6
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; FLATSCRW64-NEXT: {{ $}}
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; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02
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; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
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; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
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; FLATSCRW64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5
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; FLATSCRW64-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 killed renamable $sgpr4_sgpr5, $exec, implicit-def $scc
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; FLATSCRW64-NEXT: $sgpr5 = S_ADDC_U32 $sgpr32, 64, implicit-def $scc, implicit $scc
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; FLATSCRW64-NEXT: S_BITCMP1_B32 $sgpr5, 0, implicit-def $scc
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; FLATSCRW64-NEXT: $sgpr5 = S_BITSET0_B32 0, $sgpr5
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; FLATSCRW64-NEXT: renamable $sgpr4 = S_ADDC_U32 killed $sgpr5, $sgpr6, implicit-def $scc, implicit $scc
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; FLATSCRW64-NEXT: SI_RETURN implicit $sgpr4
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;
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; FLATSCRW32-LABEL: name: s_addc_u32_fi_after_and_scc_producer
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; FLATSCRW32: liveins: $sgpr4, $sgpr5, $sgpr6
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; FLATSCRW32-NEXT: {{ $}}
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; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02
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; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
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; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
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; FLATSCRW32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5
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; FLATSCRW32-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 killed renamable $sgpr4_sgpr5, $exec, implicit-def $scc
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; FLATSCRW32-NEXT: $sgpr5 = S_ADDC_U32 $sgpr32, 64, implicit-def $scc, implicit $scc
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; FLATSCRW32-NEXT: S_BITCMP1_B32 $sgpr5, 0, implicit-def $scc
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; FLATSCRW32-NEXT: $sgpr5 = S_BITSET0_B32 0, $sgpr5
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; FLATSCRW32-NEXT: renamable $sgpr4 = S_ADDC_U32 killed $sgpr5, $sgpr6, implicit-def $scc, implicit $scc
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; FLATSCRW32-NEXT: SI_RETURN implicit $sgpr4
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;
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; MUBUF-LABEL: name: s_addc_u32_fi_after_and_scc_producer
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; MUBUF: liveins: $sgpr4, $sgpr5, $sgpr6
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; MUBUF-NEXT: {{ $}}
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; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6
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; MUBUF-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32
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; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4
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; MUBUF-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5
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; MUBUF-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 killed renamable $sgpr4_sgpr5, $exec, implicit-def $scc
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; MUBUF-NEXT: $sgpr5 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc
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; MUBUF-NEXT: $sgpr5 = S_ADD_I32 killed $sgpr5, 64, implicit-def $scc
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; MUBUF-NEXT: renamable $sgpr4 = S_ADDC_U32 killed $sgpr5, $sgpr6, implicit-def $scc, implicit $scc
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; MUBUF-NEXT: SI_RETURN implicit $sgpr4
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renamable $sgpr4_sgpr5 = S_AND_B64 killed renamable $sgpr4_sgpr5, $exec, implicit-def $scc
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renamable $sgpr4 = S_ADDC_U32 %stack.1, $sgpr6, implicit-def $scc, implicit $scc
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SI_RETURN implicit $sgpr4
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...
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