derek.holloway
7502bf64a4
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221 lines
8.0 KiB
LLVM
221 lines
8.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX900 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX940 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
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define void @s_add_use_fi_sgpr_offset(i32 inreg %soffset) #0 {
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; GFX7-LABEL: s_add_use_fi_sgpr_offset:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: s_mov_b32 s7, s33
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; GFX7-NEXT: s_add_i32 s33, s32, 0x7c0
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; GFX7-NEXT: s_and_b32 s33, s33, 0xfffff800
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; GFX7-NEXT: s_mov_b32 s8, s34
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; GFX7-NEXT: s_mov_b32 s34, s32
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; GFX7-NEXT: s_add_i32 s32, s32, 0x45000
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; GFX7-NEXT: s_and_b32 s4, s16, 31
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; GFX7-NEXT: s_lshr_b32 s5, s33, 6
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; GFX7-NEXT: s_addk_i32 s5, 0x120
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; GFX7-NEXT: s_lshr_b32 s6, s33, 6
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; GFX7-NEXT: s_add_i32 s6, s6, 16
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; GFX7-NEXT: ;;#ASMSTART
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; GFX7-NEXT: ; use s5
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; GFX7-NEXT: ;;#ASMEND
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; GFX7-NEXT: s_lshr_b32 s5, s33, 6
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; GFX7-NEXT: s_addk_i32 s5, 0x120
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; GFX7-NEXT: s_or_b32 s4, s4, s5
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; GFX7-NEXT: ;;#ASMSTART
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; GFX7-NEXT: ; use s4
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; GFX7-NEXT: ;;#ASMEND
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; GFX7-NEXT: s_mov_b32 s32, s34
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; GFX7-NEXT: s_mov_b32 s34, s8
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; GFX7-NEXT: s_mov_b32 s33, s7
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX8-LABEL: s_add_use_fi_sgpr_offset:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: s_mov_b32 s7, s33
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; GFX8-NEXT: s_add_i32 s33, s32, 0x7c0
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; GFX8-NEXT: s_and_b32 s33, s33, 0xfffff800
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; GFX8-NEXT: s_mov_b32 s8, s34
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; GFX8-NEXT: s_mov_b32 s34, s32
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; GFX8-NEXT: s_add_i32 s32, s32, 0x45000
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; GFX8-NEXT: s_and_b32 s4, s16, 31
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; GFX8-NEXT: s_lshr_b32 s5, s33, 6
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; GFX8-NEXT: s_addk_i32 s5, 0x120
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; GFX8-NEXT: s_lshr_b32 s6, s33, 6
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; GFX8-NEXT: s_add_i32 s6, s6, 16
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; GFX8-NEXT: ;;#ASMSTART
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; GFX8-NEXT: ; use s5
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; GFX8-NEXT: ;;#ASMEND
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; GFX8-NEXT: s_lshr_b32 s5, s33, 6
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; GFX8-NEXT: s_addk_i32 s5, 0x120
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; GFX8-NEXT: s_or_b32 s4, s4, s5
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; GFX8-NEXT: ;;#ASMSTART
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; GFX8-NEXT: ; use s4
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; GFX8-NEXT: ;;#ASMEND
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; GFX8-NEXT: s_mov_b32 s32, s34
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; GFX8-NEXT: s_mov_b32 s34, s8
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; GFX8-NEXT: s_mov_b32 s33, s7
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; GFX8-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX900-LABEL: s_add_use_fi_sgpr_offset:
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; GFX900: ; %bb.0:
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; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX900-NEXT: s_mov_b32 s7, s33
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; GFX900-NEXT: s_add_i32 s33, s32, 0x7c0
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; GFX900-NEXT: s_and_b32 s33, s33, 0xfffff800
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; GFX900-NEXT: s_mov_b32 s8, s34
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; GFX900-NEXT: s_mov_b32 s34, s32
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; GFX900-NEXT: s_add_i32 s32, s32, 0x45000
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; GFX900-NEXT: s_and_b32 s4, s16, 31
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; GFX900-NEXT: s_lshr_b32 s5, s33, 6
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; GFX900-NEXT: s_addk_i32 s5, 0x120
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; GFX900-NEXT: s_lshr_b32 s6, s33, 6
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; GFX900-NEXT: s_add_i32 s6, s6, 16
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; GFX900-NEXT: ;;#ASMSTART
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; GFX900-NEXT: ; use s5
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; GFX900-NEXT: ;;#ASMEND
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; GFX900-NEXT: s_lshr_b32 s5, s33, 6
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; GFX900-NEXT: s_addk_i32 s5, 0x120
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; GFX900-NEXT: s_or_b32 s4, s4, s5
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; GFX900-NEXT: ;;#ASMSTART
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; GFX900-NEXT: ; use s4
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; GFX900-NEXT: ;;#ASMEND
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; GFX900-NEXT: s_mov_b32 s32, s34
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; GFX900-NEXT: s_mov_b32 s34, s8
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; GFX900-NEXT: s_mov_b32 s33, s7
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; GFX900-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: s_add_use_fi_sgpr_offset:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_mov_b32 s7, s33
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; GFX10-NEXT: s_add_i32 s33, s32, 0x3e0
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; GFX10-NEXT: s_mov_b32 s8, s34
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; GFX10-NEXT: s_and_b32 s33, s33, 0xfffffc00
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; GFX10-NEXT: s_mov_b32 s34, s32
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; GFX10-NEXT: s_add_i32 s32, s32, 0x22800
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; GFX10-NEXT: s_and_b32 s4, s16, 31
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; GFX10-NEXT: s_lshr_b32 s5, s33, 5
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; GFX10-NEXT: s_mov_b32 s32, s34
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; GFX10-NEXT: s_addk_i32 s5, 0x120
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; GFX10-NEXT: s_lshr_b32 s6, s33, 5
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; GFX10-NEXT: s_mov_b32 s34, s8
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; GFX10-NEXT: s_add_i32 s6, s6, 16
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; GFX10-NEXT: s_lshr_b32 s9, s33, 5
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; GFX10-NEXT: ;;#ASMSTART
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; GFX10-NEXT: ; use s5
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; GFX10-NEXT: ;;#ASMEND
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; GFX10-NEXT: s_addk_i32 s9, 0x120
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; GFX10-NEXT: s_or_b32 s4, s4, s9
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; GFX10-NEXT: ;;#ASMSTART
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; GFX10-NEXT: ; use s4
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; GFX10-NEXT: ;;#ASMEND
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; GFX10-NEXT: s_mov_b32 s33, s7
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX940-LABEL: s_add_use_fi_sgpr_offset:
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; GFX940: ; %bb.0:
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; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX940-NEXT: s_mov_b32 s3, s33
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; GFX940-NEXT: s_add_i32 s33, s32, 31
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; GFX940-NEXT: s_andn2_b32 s33, s33, 31
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; GFX940-NEXT: s_mov_b32 s4, s34
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; GFX940-NEXT: s_mov_b32 s34, s32
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; GFX940-NEXT: s_addk_i32 s32, 0x1140
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; GFX940-NEXT: s_and_b32 s0, s0, 31
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; GFX940-NEXT: s_add_i32 s2, s33, 0x120
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; GFX940-NEXT: s_mov_b32 s1, s2
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; GFX940-NEXT: s_add_i32 s5, s33, 16
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; GFX940-NEXT: s_mov_b32 s2, s5
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; GFX940-NEXT: ;;#ASMSTART
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; GFX940-NEXT: ; use s1
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; GFX940-NEXT: ;;#ASMEND
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; GFX940-NEXT: s_add_i32 s1, s33, 0x120
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; GFX940-NEXT: s_or_b32 s0, s0, s1
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; GFX940-NEXT: ;;#ASMSTART
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; GFX940-NEXT: ; use s0
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; GFX940-NEXT: ;;#ASMEND
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; GFX940-NEXT: s_mov_b32 s32, s34
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; GFX940-NEXT: s_mov_b32 s34, s4
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; GFX940-NEXT: s_mov_b32 s33, s3
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; GFX940-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: s_add_use_fi_sgpr_offset:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_mov_b32 s3, s33
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; GFX11-NEXT: s_add_i32 s33, s32, 31
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; GFX11-NEXT: s_mov_b32 s4, s34
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; GFX11-NEXT: s_and_not1_b32 s33, s33, 31
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; GFX11-NEXT: s_mov_b32 s34, s32
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; GFX11-NEXT: s_addk_i32 s32, 0x1140
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; GFX11-NEXT: s_and_b32 s0, s0, 31
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; GFX11-NEXT: s_add_i32 s2, s33, 0x120
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; GFX11-NEXT: s_add_i32 s5, s33, 16
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; GFX11-NEXT: s_mov_b32 s1, s2
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; GFX11-NEXT: s_mov_b32 s2, s5
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; GFX11-NEXT: s_add_i32 s5, s33, 0x120
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use s1
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_or_b32 s0, s0, s5
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; GFX11-NEXT: ;;#ASMSTART
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; GFX11-NEXT: ; use s0
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; GFX11-NEXT: ;;#ASMEND
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; GFX11-NEXT: s_mov_b32 s32, s34
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; GFX11-NEXT: s_mov_b32 s34, s4
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; GFX11-NEXT: s_mov_b32 s33, s3
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: s_add_use_fi_sgpr_offset:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_mov_b32 s3, s33
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; GFX12-NEXT: s_add_co_i32 s33, s32, 31
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; GFX12-NEXT: s_mov_b32 s4, s34
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; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
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; GFX12-NEXT: s_and_not1_b32 s33, s33, 31
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; GFX12-NEXT: s_mov_b32 s34, s32
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; GFX12-NEXT: s_addk_co_i32 s32, 0x1140
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; GFX12-NEXT: s_and_b32 s0, s0, 31
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; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
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; GFX12-NEXT: s_add_co_i32 s2, s33, 0x100
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; GFX12-NEXT: s_add_co_i32 s5, s33, 0x100
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; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
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; GFX12-NEXT: s_mov_b32 s1, s2
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; GFX12-NEXT: s_mov_b32 s2, s33
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; GFX12-NEXT: s_or_b32 s0, s0, s5
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; GFX12-NEXT: ;;#ASMSTART
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; GFX12-NEXT: ; use s1
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; GFX12-NEXT: ;;#ASMEND
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; GFX12-NEXT: ;;#ASMSTART
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; GFX12-NEXT: ; use s0
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; GFX12-NEXT: ;;#ASMEND
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; GFX12-NEXT: s_mov_b32 s32, s34
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; GFX12-NEXT: s_mov_b32 s34, s4
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; GFX12-NEXT: s_mov_b32 s33, s3
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; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%filler = alloca [256 x i8], align 16, addrspace(5)
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%alloca = alloca [4096 x i8], align 32, addrspace(5)
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%soffset.and = and i32 %soffset, 31
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call void asm sideeffect "; use $0", "s,s"(ptr addrspace(5) %alloca, ptr addrspace(5) %filler)
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%gep = getelementptr inbounds nuw [4096 x i8], ptr addrspace(5) %alloca, i32 0, i32 %soffset.and
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call void asm sideeffect "; use $0", "s"(ptr addrspace(5) %gep)
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ret void
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}
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