derek.holloway
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114 lines
4.8 KiB
YAML
114 lines
4.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=amdgpu-lower-vgpr-encoding -o - %s | FileCheck %s
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# Test handling of the GFX1250 hardware hazard where S_SET_VGPR_MSB immediately
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# after S_SETREG_IMM32_B32 (MODE) is silently dropped.
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#
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# AMDGPULowerVGPREncoding may place S_SET_VGPR_MSB after S_SETREG_IMM32_B32
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# (MODE) in Case 2 (size > 12). It inserts S_NOPs between them to prevent
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# the hazard.
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---
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# Case 2 mismatch: setreg (size=16) with imm32[12:19] that doesn't match
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# current VGPR MSB. AMDGPULowerVGPREncoding inserts S_NOP + S_SET_VGPR_MSB
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# after the setreg.
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name: setreg_mode_size_gt_12_mismatch
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_mode_size_gt_12_mismatch
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; CHECK: S_SET_VGPR_MSB 64, implicit-def $mode
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; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
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; CHECK-NEXT: S_SETREG_IMM32_B32 6844, 30721, implicit-def $mode, implicit $mode
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; CHECK-NEXT: S_NOP 0
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; CHECK-NEXT: S_SET_VGPR_MSB 16384, implicit-def $mode
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; CHECK-NEXT: SI_RETURN
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$vgpr256 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
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; hwreg(MODE, 0, 16): simm16 = 0x7801 = 30721
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; imm32 = 0x23ABC = 146108 (bits 12:19 = 0x23, doesn't match VGPR MSB mode)
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S_SETREG_IMM32_B32 146108, 30721, implicit-def $mode, implicit $mode
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SI_RETURN
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...
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---
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# Case 2 with different next MSB: setreg (size=16) with imm32[12:19] that
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# doesn't match current VGPR MSB. S_NOP + S_SET_VGPR_MSB are inserted for the
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# next VALU (v512/v513).
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name: setreg_mode_size_gt_12_matches_next
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_mode_size_gt_12_matches_next
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; CHECK: S_SET_VGPR_MSB 65, implicit-def $mode
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; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 undef $vgpr257, implicit $exec
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; CHECK-NEXT: S_SETREG_IMM32_B32 23228, 30721, implicit-def $mode, implicit $mode
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; CHECK-NEXT: S_NOP 0
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; CHECK-NEXT: S_SET_VGPR_MSB 16770, implicit-def $mode
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; CHECK-NEXT: $vgpr512 = V_MOV_B32_e32 undef $vgpr513, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0
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$vgpr256 = V_MOV_B32_e32 undef $vgpr257, implicit $exec
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; hwreg(MODE, 0, 16): simm16 = 0x7801 = 30721
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; imm32 = 0xAABC = 43708 (bits 12:19 = 0xA = 10, matches next MSB for v512/v513)
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S_SETREG_IMM32_B32 43708, 30721, implicit-def $mode, implicit $mode
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$vgpr512 = V_MOV_B32_e32 undef $vgpr513, implicit $exec
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S_ENDPGM 0
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...
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---
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# No hazard: S_SETREG_IMM32_B32 targeting non-MODE register.
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name: setreg_non_mode_no_hazard
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_non_mode_no_hazard
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; CHECK: S_SET_VGPR_MSB 64, implicit-def $mode
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; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
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; CHECK-NEXT: S_SETREG_IMM32_B32 0, 2178, implicit-def $mode, implicit $mode
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; CHECK-NEXT: S_SET_VGPR_MSB 16384, implicit-def $mode
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; CHECK-NEXT: $vgpr0 = V_ADD_F32_e32 undef $vgpr1, undef $vgpr2, implicit $exec, implicit $mode
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; CHECK-NEXT: S_ENDPGM 0
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$vgpr256 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
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; hwreg(STATUS, 2, 2): simm16 = 2 | (2 << 6) | (1 << 11) = 0x882 = 2178
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S_SETREG_IMM32_B32 0, 2178, implicit-def $mode, implicit $mode
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$vgpr0 = V_ADD_F32_e32 undef $vgpr1, undef $vgpr2, implicit $exec, implicit $mode
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S_ENDPGM 0
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...
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---
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# Case 2 but no high VGPRs before setreg.
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name: setreg_mode_size_gt_12_no_high_vgpr
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_mode_size_gt_12_no_high_vgpr
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; CHECK: $vgpr0 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
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; CHECK-NEXT: S_SETREG_IMM32_B32 2748, 30721, implicit-def $mode, implicit $mode
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; CHECK-NEXT: SI_RETURN
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$vgpr0 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
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; hwreg(MODE, 0, 16): simm16 = 0x7801 = 30721
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S_SETREG_IMM32_B32 146108, 30721, implicit-def $mode, implicit $mode
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SI_RETURN
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...
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---
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# Case 2 with high VGPR only AFTER setreg: setreg (size=16) with low VGPRs
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# before but high VGPRs after. AMDGPULowerVGPREncoding inserts S_NOP +
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# S_SET_VGPR_MSB before the next VALU (which is right after setreg).
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name: setreg_mode_size_gt_12_high_vgpr_after
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: setreg_mode_size_gt_12_high_vgpr_after
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; CHECK: $vgpr0 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
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; CHECK-NEXT: S_SETREG_IMM32_B32 2748, 30721, implicit-def $mode, implicit $mode
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; CHECK-NEXT: S_NOP 0
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; CHECK-NEXT: S_SET_VGPR_MSB 64, implicit-def $mode
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; CHECK-NEXT: $vgpr256 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0
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$vgpr0 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
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; hwreg(MODE, 0, 16): simm16 = 0x7801 = 30721
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S_SETREG_IMM32_B32 146108, 30721, implicit-def $mode, implicit $mode
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$vgpr256 = V_MOV_B32_e32 undef $sgpr0, implicit $exec
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S_ENDPGM 0
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...
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