derek.holloway
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354 lines
16 KiB
LLVM
354 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefix=SDAG-REAL16 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefix=SDAG-FAKE16 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefix=GISEL-REAL16 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefix=GISEL-FAKE16 %s
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declare i16 @llvm.amdgcn.sat.pk4.i4.i8(i32) #0
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declare i16 @llvm.amdgcn.sat.pk4.u4.u8(i32) #0
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define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
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; SDAG-REAL16-LABEL: sat_pk4_i4_i8_f32_v:
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; SDAG-REAL16: ; %bb.0:
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; SDAG-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; SDAG-REAL16-NEXT: v_nop
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; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-REAL16-NEXT: s_clause 0x1
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; SDAG-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
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; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
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; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
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; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
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; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
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; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
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; SDAG-REAL16-NEXT: s_endpgm
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;
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; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_v:
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; SDAG-FAKE16: ; %bb.0:
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; SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; SDAG-FAKE16-NEXT: v_nop
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; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-FAKE16-NEXT: s_clause 0x1
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; SDAG-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
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; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
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; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
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; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
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; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, s2
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; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
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; SDAG-FAKE16-NEXT: s_endpgm
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;
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; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_v:
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; GISEL-REAL16: ; %bb.0:
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; GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GISEL-REAL16-NEXT: v_nop
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; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GISEL-REAL16-NEXT: s_clause 0x1
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; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
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; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
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; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
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; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
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; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
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; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
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; GISEL-REAL16-NEXT: s_endpgm
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;
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; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_v:
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; GISEL-FAKE16: ; %bb.0:
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; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GISEL-FAKE16-NEXT: v_nop
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; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GISEL-FAKE16-NEXT: s_clause 0x1
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; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
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; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
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; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
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; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, s2
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; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
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; GISEL-FAKE16-NEXT: s_endpgm
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%cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 %src) #0
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store i16 %cvt, ptr %out, align 2
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ret void
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}
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define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
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; SDAG-REAL16-LABEL: sat_pk4_i4_i8_f32_s:
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; SDAG-REAL16: ; %bb.0:
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; SDAG-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; SDAG-REAL16-NEXT: v_nop
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; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
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; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
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; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s8
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; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
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; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
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; SDAG-REAL16-NEXT: s_endpgm
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;
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; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_s:
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; SDAG-FAKE16: ; %bb.0:
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; SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; SDAG-FAKE16-NEXT: v_nop
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; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
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; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
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; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, s8
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; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
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; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
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; SDAG-FAKE16-NEXT: s_endpgm
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;
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; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_s:
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; GISEL-REAL16: ; %bb.0:
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; GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GISEL-REAL16-NEXT: v_nop
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; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GISEL-REAL16-NEXT: s_clause 0x1
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; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
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; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
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; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
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; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
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; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
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; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
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; GISEL-REAL16-NEXT: s_endpgm
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;
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; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_s:
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; GISEL-FAKE16: ; %bb.0:
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; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GISEL-FAKE16-NEXT: v_nop
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; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GISEL-FAKE16-NEXT: s_clause 0x1
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; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
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; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
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; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
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; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, s2
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; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
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; GISEL-FAKE16-NEXT: s_endpgm
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%cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 %src) #0
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store i16 %cvt, ptr %out, align 2
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ret void
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}
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define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
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; SDAG-REAL16-LABEL: sat_pk4_i4_i8_f32_i:
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; SDAG-REAL16: ; %bb.0:
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; SDAG-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; SDAG-REAL16-NEXT: v_nop
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; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
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; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
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; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, 0x64
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; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
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; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
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; SDAG-REAL16-NEXT: s_endpgm
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;
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; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_i:
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; SDAG-FAKE16: ; %bb.0:
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; SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; SDAG-FAKE16-NEXT: v_nop
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; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
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; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
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; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, 0x64
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; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
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; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
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; SDAG-FAKE16-NEXT: s_endpgm
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;
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; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_i:
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; GISEL-REAL16: ; %bb.0:
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; GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GISEL-REAL16-NEXT: v_nop
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; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
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; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, 0x64
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; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
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; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
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; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
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; GISEL-REAL16-NEXT: s_endpgm
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;
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; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_i:
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; GISEL-FAKE16: ; %bb.0:
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; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GISEL-FAKE16-NEXT: v_nop
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; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
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; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, 0x64
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; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
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; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
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; GISEL-FAKE16-NEXT: s_endpgm
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%cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 100) #0
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store i16 %cvt, ptr %out, align 2
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ret void
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}
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define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
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; SDAG-REAL16-LABEL: sat_pk4_u4_u8_f32_v:
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; SDAG-REAL16: ; %bb.0:
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; SDAG-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; SDAG-REAL16-NEXT: v_nop
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; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-REAL16-NEXT: s_clause 0x1
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; SDAG-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
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; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
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; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
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; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
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; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
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; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
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; SDAG-REAL16-NEXT: s_endpgm
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;
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; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_v:
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; SDAG-FAKE16: ; %bb.0:
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; SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; SDAG-FAKE16-NEXT: v_nop
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; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-FAKE16-NEXT: s_clause 0x1
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; SDAG-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
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; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
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; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
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; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
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; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, s2
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; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
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; SDAG-FAKE16-NEXT: s_endpgm
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;
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; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_v:
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; GISEL-REAL16: ; %bb.0:
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; GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GISEL-REAL16-NEXT: v_nop
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; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GISEL-REAL16-NEXT: s_clause 0x1
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; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
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; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
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; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
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; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
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; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
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; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
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; GISEL-REAL16-NEXT: s_endpgm
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;
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; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_v:
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; GISEL-FAKE16: ; %bb.0:
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; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GISEL-FAKE16-NEXT: v_nop
|
|
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GISEL-FAKE16-NEXT: s_clause 0x1
|
|
; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
|
|
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
|
|
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
|
|
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, s2
|
|
; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
|
|
; GISEL-FAKE16-NEXT: s_endpgm
|
|
%cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 %src) #0
|
|
store i16 %cvt, ptr %out, align 2
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
|
|
; SDAG-REAL16-LABEL: sat_pk4_u4_u8_f32_s:
|
|
; SDAG-REAL16: ; %bb.0:
|
|
; SDAG-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; SDAG-REAL16-NEXT: v_nop
|
|
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
|
|
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
|
|
; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s8
|
|
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
|
|
; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
|
|
; SDAG-REAL16-NEXT: s_endpgm
|
|
;
|
|
; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_s:
|
|
; SDAG-FAKE16: ; %bb.0:
|
|
; SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; SDAG-FAKE16-NEXT: v_nop
|
|
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
|
|
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
|
|
; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, s8
|
|
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
|
|
; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
|
|
; SDAG-FAKE16-NEXT: s_endpgm
|
|
;
|
|
; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_s:
|
|
; GISEL-REAL16: ; %bb.0:
|
|
; GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GISEL-REAL16-NEXT: v_nop
|
|
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GISEL-REAL16-NEXT: s_clause 0x1
|
|
; GISEL-REAL16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
|
|
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
|
|
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
|
|
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
|
|
; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
|
|
; GISEL-REAL16-NEXT: s_endpgm
|
|
;
|
|
; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_s:
|
|
; GISEL-FAKE16: ; %bb.0:
|
|
; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GISEL-FAKE16-NEXT: v_nop
|
|
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GISEL-FAKE16-NEXT: s_clause 0x1
|
|
; GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x0 nv
|
|
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 nv
|
|
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
|
|
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, s2
|
|
; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
|
|
; GISEL-FAKE16-NEXT: s_endpgm
|
|
%cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 %src) #0
|
|
store i16 %cvt, ptr %out, align 2
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
|
|
; SDAG-REAL16-LABEL: sat_pk4_u4_u8_f32_i:
|
|
; SDAG-REAL16: ; %bb.0:
|
|
; SDAG-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; SDAG-REAL16-NEXT: v_nop
|
|
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
|
|
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
|
|
; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, 0x64
|
|
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
|
|
; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
|
|
; SDAG-REAL16-NEXT: s_endpgm
|
|
;
|
|
; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_i:
|
|
; SDAG-FAKE16: ; %bb.0:
|
|
; SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; SDAG-FAKE16-NEXT: v_nop
|
|
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
|
|
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
|
|
; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, 0x64
|
|
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
|
|
; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
|
|
; SDAG-FAKE16-NEXT: s_endpgm
|
|
;
|
|
; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_i:
|
|
; GISEL-REAL16: ; %bb.0:
|
|
; GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GISEL-REAL16-NEXT: v_nop
|
|
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
|
|
; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, 0x64
|
|
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
|
|
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
|
|
; GISEL-REAL16-NEXT: s_endpgm
|
|
;
|
|
; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_i:
|
|
; GISEL-FAKE16: ; %bb.0:
|
|
; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GISEL-FAKE16-NEXT: v_nop
|
|
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
|
|
; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, 0x64
|
|
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
|
|
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
|
|
; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
|
|
; GISEL-FAKE16-NEXT: s_endpgm
|
|
%cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 100) #0
|
|
store i16 %cvt, ptr %out, align 2
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind memory(none) }
|
|
attributes #1 = { nounwind }
|