derek.holloway
7502bf64a4
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164 lines
6.0 KiB
LLVM
164 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=SI %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=VI %s
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; RUN: llc -mtriple=amdgcn -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=SI-GISEL %s
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; RUN: llc -mtriple=amdgcn -global-isel=1 -new-reg-bank-select -mcpu=tonga < %s | FileCheck -check-prefixes=VI-GISEL %s
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declare float @llvm.amdgcn.rsq.clamp.f32(float) #1
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declare double @llvm.amdgcn.rsq.clamp.f64(double) #1
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define amdgpu_kernel void @rsq_clamp_f32(ptr addrspace(1) %out, float %src) #0 {
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; SI-LABEL: rsq_clamp_f32:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s6, s[4:5], 0xb
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; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: v_rsq_clamp_f32_e32 v0, s6
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; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: rsq_clamp_f32:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_rsq_f32_e32 v0, s0
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; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; VI-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v0
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; VI-NEXT: v_max_f32_e32 v2, 0xff7fffff, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v0, s0
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; VI-NEXT: v_mov_b32_e32 v1, s1
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_endpgm
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;
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; SI-GISEL-LABEL: rsq_clamp_f32:
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; SI-GISEL: ; %bb.0:
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; SI-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
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; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-GISEL-NEXT: s_mov_b32 s2, -1
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; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; SI-GISEL-NEXT: v_rsq_clamp_f32_e32 v0, s3
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; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
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; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-GISEL-NEXT: s_endpgm
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;
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; VI-GISEL-LABEL: rsq_clamp_f32:
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; VI-GISEL: ; %bb.0:
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; VI-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
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; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; VI-GISEL-NEXT: v_rsq_f32_e32 v0, s0
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; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; VI-GISEL-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v0
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; VI-GISEL-NEXT: v_max_f32_e32 v2, 0xff7fffff, v0
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; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
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; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
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; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
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; VI-GISEL-NEXT: s_endpgm
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%rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float %src)
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store float %rsq_clamp, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @rsq_clamp_f64(ptr addrspace(1) %out, double %src) #0 {
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; SI-LABEL: rsq_clamp_f64:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s1
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; SI-NEXT: v_rsq_clamp_f64_e32 v[0:1], s[2:3]
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: rsq_clamp_f64:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_rsq_f64_e32 v[0:1], s[2:3]
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; VI-NEXT: s_mov_b32 s3, 0x7fefffff
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: v_mov_b32_e32 v2, s0
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; VI-NEXT: v_mov_b32_e32 v3, s1
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; VI-NEXT: v_min_f64 v[0:1], v[0:1], s[2:3]
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; VI-NEXT: s_mov_b32 s3, 0xffefffff
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; VI-NEXT: v_max_f64 v[0:1], v[0:1], s[2:3]
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; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
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; VI-NEXT: s_endpgm
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;
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; SI-GISEL-LABEL: rsq_clamp_f64:
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; SI-GISEL: ; %bb.0:
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; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; SI-GISEL-NEXT: v_rsq_clamp_f64_e32 v[0:1], s[2:3]
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; SI-GISEL-NEXT: s_mov_b32 s2, -1
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; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
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; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; SI-GISEL-NEXT: s_endpgm
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;
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; VI-GISEL-LABEL: rsq_clamp_f64:
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; VI-GISEL: ; %bb.0:
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; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-GISEL-NEXT: v_mov_b32_e32 v2, -1
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; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fefffff
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; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; VI-GISEL-NEXT: v_rsq_f64_e32 v[0:1], s[2:3]
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; VI-GISEL-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3]
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; VI-GISEL-NEXT: v_mov_b32_e32 v2, -1
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; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xffefffff
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; VI-GISEL-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3]
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; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
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; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
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; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
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; VI-GISEL-NEXT: s_endpgm
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%rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src)
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store double %rsq_clamp, ptr addrspace(1) %out
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ret void
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}
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; With SDAG, poison folding happens in target specific combine. With GISel this
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; only happens as part of InstCombine so is not tested here.
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define amdgpu_kernel void @rsq_clamp_undef_f32(ptr addrspace(1) %out) #0 {
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; SI-LABEL: rsq_clamp_undef_f32:
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; SI: ; %bb.0:
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: rsq_clamp_undef_f32:
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; VI: ; %bb.0:
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; VI-NEXT: s_endpgm
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;
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; SI-GISEL-LABEL: rsq_clamp_undef_f32:
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; SI-GISEL: ; %bb.0:
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; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; SI-GISEL-NEXT: v_rsq_clamp_f32_e32 v0, s0
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; SI-GISEL-NEXT: s_mov_b32 s2, -1
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; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
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; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; SI-GISEL-NEXT: s_endpgm
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;
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; VI-GISEL-LABEL: rsq_clamp_undef_f32:
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; VI-GISEL: ; %bb.0:
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; VI-GISEL-NEXT: v_rsq_f32_e32 v0, s0
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; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; VI-GISEL-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v0
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; VI-GISEL-NEXT: v_max_f32_e32 v2, 0xff7fffff, v0
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; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
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; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
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; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
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; VI-GISEL-NEXT: s_endpgm
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%rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float poison)
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store float %rsq_clamp, ptr addrspace(1) %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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