derek.holloway
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67 lines
3.1 KiB
LLVM
67 lines
3.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck %s --check-prefixes=GCN,GFX9,GFX906
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; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck %s --check-prefixes=GCN,GFX9,GFX942-SDAG
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; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -global-isel -new-reg-bank-select < %s | FileCheck %s --check-prefixes=GCN,GFX9,GFX942-GISEL
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck %s --check-prefixes=GCN,GFX10
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck %s --check-prefixes=GCN,GFX10
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declare i32 @llvm.amdgcn.udot2(<2 x i16> %a, <2 x i16> %b, i32 %c, i1 %clamp)
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declare i32 @llvm.amdgcn.workitem.id.x()
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; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_clamp:
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; GFX9: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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; GFX10: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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define amdgpu_kernel void @test_llvm_amdgcn_udot2_clamp(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load <2 x i16>, ptr addrspace(1) %a
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%b.val = load <2 x i16>, ptr addrspace(1) %b
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%c.val = load i32, ptr addrspace(1) %c
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%r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 1)
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store i32 %r.val, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_no_clamp:
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; GFX9: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
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; GFX10: v_dot2_u32_u16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
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define amdgpu_kernel void @test_llvm_amdgcn_udot2_no_clamp(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load <2 x i16>, ptr addrspace(1) %a
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%b.val = load <2 x i16>, ptr addrspace(1) %b
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%c.val = load i32, ptr addrspace(1) %c
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%r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 0)
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store i32 %r.val, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}test_llvm_amdgcn_udot2_op_sel:
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; GFX906: v_dot2_u32_u16 v{{[0-9]+}}, 1, v{{[0-9]+}}, s{{[0-9]+}} op_sel:[0,1,0] op_sel_hi:[0,0,1]{{$}}
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; GFX942-SDAG: s_mov_b32 [[K:s[0-9]+]], 0x10001
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; GFX942-SDAG: v_dot2_u32_u16 v{{[0-9]+}}, [[K]], v{{[0-9]+}}, v{{[0-9]+}}{{$}}
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; GFX942-GISEL: v_mov_b32_e32 [[K:v[0-9]+]], 0x10001
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; GFX942-GISEL: v_dot2_u32_u16 v{{[0-9]+}}, [[K]], v{{[0-9]+}}, s{{[0-9]+}}{{$}}
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; GFX10: v_dot2_u32_u16 v{{[0-9]+}}, 1, v{{[0-9]+}}, s{{[0-9]+}} op_sel:[0,1,0] op_sel_hi:[0,0,1]{{$}}
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define amdgpu_kernel void @test_llvm_amdgcn_udot2_op_sel(
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ptr addrspace(1) %r,
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ptr addrspace(1) %b,
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i32 %c) {
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entry:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%b.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %b, i32 %id
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%b.val = load <2 x i16>, ptr addrspace(1) %b.gep
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%b.elt0 = extractelement <2 x i16> %b.val, i32 0
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%b.elt1 = extractelement <2 x i16> %b.val, i32 1
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%b0 = insertelement <2 x i16> poison, i16 %b.elt1, i32 0
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%b1 = insertelement <2 x i16> %b0, i16 %b.elt0, i32 1
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%r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> <i16 1, i16 1>, <2 x i16> %b1, i32 %c, i1 0)
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store i32 %r.val, ptr addrspace(1) %r
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ret void
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}
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