derek.holloway
7502bf64a4
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37 lines
1.3 KiB
LLVM
37 lines
1.3 KiB
LLVM
; RUN: llc -mcpu=kaveri -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s
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; Check that when mubuf addr64 instruction is handled in moveToVALU
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; from the pointer, dead register writes are not emitted.
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; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32
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; GCN-LABEL: {{^}}clobber_vgpr_pair_pointer_add:
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; GCN-DAG: buffer_load_dwordx2 v[[[LDPTRLO:[0-9]+]]:[[LDPTRHI:[0-9]+]]]
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; GCN-DAG: s_load_dwordx2 s[[[ARG1LO:[0-9]+]]:[[ARG1HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
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; GCN-DAG: v_mov_b32_e32 v[[VARG1LO:[0-9]+]], s[[ARG1LO]]
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; GCN-DAG: v_mov_b32_e32 v[[VARG1HI:[0-9]+]], s[[ARG1HI]]
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; GCN-NOT: v_mov_b32
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; GCN-NOT: v_mov_b32
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; GCN: v_add_i32_e32 v[[PTRLO:[0-9]+]], vcc, v[[LDPTRLO]], v[[VARG1LO]]
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; GCN: v_addc_u32_e32 v[[PTRHI:[0-9]+]], vcc, v[[LDPTRHI]], v[[VARG1HI]]
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; GCN: buffer_load_ubyte v{{[0-9]+}}, v[[[PTRLO]]:[[PTRHI]]],
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define amdgpu_kernel void @clobber_vgpr_pair_pointer_add(i64 %arg1, [8 x i32], ptr addrspace(1) %ptrarg, i32 %arg3) #0 {
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bb:
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%tmp = icmp sgt i32 %arg3, 0
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br i1 %tmp, label %bb4, label %bb17
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bb4:
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%tmp14 = load volatile ptr addrspace(1), ptr addrspace(1) %ptrarg
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%tmp15 = getelementptr inbounds i8, ptr addrspace(1) %tmp14, i64 %arg1
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%tmp16 = load volatile i8, ptr addrspace(1) %tmp15
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br label %bb17
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bb17:
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ret void
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}
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attributes #0 = { nounwind }
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