derek.holloway
7502bf64a4
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40 lines
1.2 KiB
LLVM
40 lines
1.2 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=BOTH %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI -check-prefix=BOTH %s
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; BOTH-LABEL: {{^}}s_rotl_i64:
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; BOTH-DAG: s_lshl_b64
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; BOTH-DAG: s_sub_i32
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; BOTH-DAG: s_lshr_b64
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; BOTH: s_or_b64
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; BOTH: s_endpgm
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define amdgpu_kernel void @s_rotl_i64(ptr addrspace(1) %in, i64 %x, i64 %y) {
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entry:
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%0 = shl i64 %x, %y
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%1 = sub i64 64, %y
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%2 = lshr i64 %x, %1
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%3 = or i64 %0, %2
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store i64 %3, ptr addrspace(1) %in
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ret void
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}
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; BOTH-LABEL: {{^}}v_rotl_i64:
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; SI-DAG: v_lshl_b64
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; VI-DAG: v_lshlrev_b64
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; BOTH-DAG: v_sub_{{[iu]}}32
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; SI: v_lshr_b64
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; VI: v_lshrrev_b64
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; BOTH: v_or_b32
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; BOTH: v_or_b32
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; BOTH: s_endpgm
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define amdgpu_kernel void @v_rotl_i64(ptr addrspace(1) %in, ptr addrspace(1) %xptr, ptr addrspace(1) %yptr) {
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entry:
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%x = load i64, ptr addrspace(1) %xptr, align 8
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%y = load i64, ptr addrspace(1) %yptr, align 8
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%tmp0 = shl i64 %x, %y
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%tmp1 = sub i64 64, %y
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%tmp2 = lshr i64 %x, %tmp1
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%tmp3 = or i64 %tmp0, %tmp2
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store i64 %tmp3, ptr addrspace(1) %in, align 8
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ret void
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}
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