derek.holloway
7502bf64a4
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242 lines
9.6 KiB
LLVM
242 lines
9.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefix=GCN %s
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; The first 64 SGPR spills can go to a VGPR, but there isn't a second
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; so some spills must be to memory. The last 16 element spill runs out of lanes at the 15th element.
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define amdgpu_kernel void @partial_no_vgprs_last_sgpr_spill(ptr addrspace(1) %out, i32 %in) #1 {
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; GCN-LABEL: partial_no_vgprs_last_sgpr_spill:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_add_u32 s0, s0, s17
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; GCN-NEXT: s_addc_u32 s1, s1, 0
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dword s4, s[8:9], 0x2
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dword s4, s[8:9], 0x2
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; def s[8:23]
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
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; GCN-NEXT: v_writelane_b32 v22, s8, 0
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; GCN-NEXT: v_writelane_b32 v22, s9, 1
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; GCN-NEXT: v_writelane_b32 v22, s10, 2
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; GCN-NEXT: v_writelane_b32 v22, s11, 3
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; GCN-NEXT: v_writelane_b32 v22, s12, 4
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; GCN-NEXT: v_writelane_b32 v22, s13, 5
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; GCN-NEXT: v_writelane_b32 v22, s14, 6
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; GCN-NEXT: v_writelane_b32 v22, s15, 7
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; GCN-NEXT: v_writelane_b32 v22, s16, 8
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; GCN-NEXT: v_writelane_b32 v22, s17, 9
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; GCN-NEXT: v_writelane_b32 v22, s18, 10
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; GCN-NEXT: v_writelane_b32 v22, s19, 11
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; GCN-NEXT: v_writelane_b32 v22, s20, 12
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; GCN-NEXT: v_writelane_b32 v22, s21, 13
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; GCN-NEXT: v_writelane_b32 v22, s22, 14
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; GCN-NEXT: v_writelane_b32 v22, s23, 15
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; def s[8:23]
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: v_writelane_b32 v22, s8, 16
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; GCN-NEXT: v_writelane_b32 v22, s9, 17
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; GCN-NEXT: v_writelane_b32 v22, s10, 18
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; GCN-NEXT: v_writelane_b32 v22, s11, 19
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; GCN-NEXT: v_writelane_b32 v22, s12, 20
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; GCN-NEXT: v_writelane_b32 v22, s13, 21
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; GCN-NEXT: v_writelane_b32 v22, s14, 22
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; GCN-NEXT: v_writelane_b32 v22, s15, 23
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; GCN-NEXT: v_writelane_b32 v22, s16, 24
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; GCN-NEXT: v_writelane_b32 v22, s17, 25
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; GCN-NEXT: v_writelane_b32 v22, s18, 26
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; GCN-NEXT: v_writelane_b32 v22, s19, 27
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; GCN-NEXT: v_writelane_b32 v22, s20, 28
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; GCN-NEXT: v_writelane_b32 v22, s21, 29
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; GCN-NEXT: v_writelane_b32 v22, s22, 30
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; GCN-NEXT: v_writelane_b32 v22, s23, 31
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; def s[8:23]
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: v_writelane_b32 v22, s8, 32
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; GCN-NEXT: v_writelane_b32 v22, s9, 33
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; GCN-NEXT: v_writelane_b32 v22, s10, 34
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; GCN-NEXT: v_writelane_b32 v22, s11, 35
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; GCN-NEXT: v_writelane_b32 v22, s12, 36
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; GCN-NEXT: v_writelane_b32 v22, s13, 37
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; GCN-NEXT: v_writelane_b32 v22, s14, 38
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; GCN-NEXT: v_writelane_b32 v22, s15, 39
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; GCN-NEXT: v_writelane_b32 v22, s16, 40
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; GCN-NEXT: v_writelane_b32 v22, s17, 41
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; GCN-NEXT: v_writelane_b32 v22, s18, 42
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; GCN-NEXT: v_writelane_b32 v22, s19, 43
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; GCN-NEXT: v_writelane_b32 v22, s20, 44
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; GCN-NEXT: v_writelane_b32 v22, s21, 45
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; GCN-NEXT: v_writelane_b32 v22, s22, 46
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; GCN-NEXT: v_writelane_b32 v22, s23, 47
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; def s[8:23]
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: v_writelane_b32 v22, s8, 48
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; GCN-NEXT: v_writelane_b32 v22, s9, 49
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; GCN-NEXT: v_writelane_b32 v22, s10, 50
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; GCN-NEXT: v_writelane_b32 v22, s11, 51
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; GCN-NEXT: v_writelane_b32 v22, s12, 52
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; GCN-NEXT: v_writelane_b32 v22, s13, 53
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; GCN-NEXT: v_writelane_b32 v22, s14, 54
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; GCN-NEXT: v_writelane_b32 v22, s15, 55
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; GCN-NEXT: v_writelane_b32 v22, s16, 56
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; GCN-NEXT: v_writelane_b32 v22, s17, 57
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; GCN-NEXT: v_writelane_b32 v22, s18, 58
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; GCN-NEXT: v_writelane_b32 v22, s19, 59
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; GCN-NEXT: v_writelane_b32 v22, s20, 60
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; GCN-NEXT: v_writelane_b32 v22, s21, 61
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; GCN-NEXT: v_writelane_b32 v22, s22, 62
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; GCN-NEXT: v_writelane_b32 v22, s23, 63
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; GCN-NEXT: s_or_saveexec_b64 s[24:25], -1
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; GCN-NEXT: buffer_store_dword v22, off, s[0:3], 0 offset:4 ; 4-byte Folded Spill
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; GCN-NEXT: s_mov_b64 exec, s[24:25]
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; def s[6:7]
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
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; GCN-NEXT: v_writelane_b32 v22, s6, 0
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; GCN-NEXT: v_writelane_b32 v22, s7, 1
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; GCN-NEXT: s_or_saveexec_b64 s[24:25], -1
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; GCN-NEXT: buffer_store_dword v22, off, s[0:3], 0 ; 4-byte Folded Spill
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; GCN-NEXT: s_mov_b64 exec, s[24:25]
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; GCN-NEXT: s_mov_b32 s5, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_cmp_eq_u32 s4, s5
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; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0
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; GCN-NEXT: s_mov_b64 s[6:7], -1
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; GCN-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
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; GCN-NEXT: s_and_b64 vcc, exec, s[4:5]
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; GCN-NEXT: s_cbranch_vccnz .LBB0_2
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; GCN-NEXT: ; %bb.1: ; %bb0
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; GCN-NEXT: s_or_saveexec_b64 s[24:25], -1
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; GCN-NEXT: buffer_load_dword v23, off, s[0:3], 0 offset:4 ; 4-byte Folded Reload
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; GCN-NEXT: s_mov_b64 exec, s[24:25]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_readlane_b32 s4, v23, 0
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; GCN-NEXT: v_readlane_b32 s5, v23, 1
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; GCN-NEXT: v_readlane_b32 s6, v23, 2
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; GCN-NEXT: v_readlane_b32 s7, v23, 3
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; GCN-NEXT: v_readlane_b32 s8, v23, 4
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; GCN-NEXT: v_readlane_b32 s9, v23, 5
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; GCN-NEXT: v_readlane_b32 s10, v23, 6
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; GCN-NEXT: v_readlane_b32 s11, v23, 7
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; GCN-NEXT: v_readlane_b32 s12, v23, 8
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; GCN-NEXT: v_readlane_b32 s13, v23, 9
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; GCN-NEXT: v_readlane_b32 s14, v23, 10
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; GCN-NEXT: v_readlane_b32 s15, v23, 11
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; GCN-NEXT: v_readlane_b32 s16, v23, 12
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; GCN-NEXT: v_readlane_b32 s17, v23, 13
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; GCN-NEXT: v_readlane_b32 s18, v23, 14
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; GCN-NEXT: v_readlane_b32 s19, v23, 15
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; GCN-NEXT: s_or_saveexec_b64 s[24:25], -1
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; GCN-NEXT: buffer_load_dword v22, off, s[0:3], 0 ; 4-byte Folded Reload
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; GCN-NEXT: s_mov_b64 exec, s[24:25]
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use s[4:19]
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: v_readlane_b32 s4, v23, 16
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; GCN-NEXT: v_readlane_b32 s5, v23, 17
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; GCN-NEXT: v_readlane_b32 s6, v23, 18
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; GCN-NEXT: v_readlane_b32 s7, v23, 19
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; GCN-NEXT: v_readlane_b32 s8, v23, 20
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; GCN-NEXT: v_readlane_b32 s9, v23, 21
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; GCN-NEXT: v_readlane_b32 s10, v23, 22
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; GCN-NEXT: v_readlane_b32 s11, v23, 23
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; GCN-NEXT: v_readlane_b32 s12, v23, 24
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; GCN-NEXT: v_readlane_b32 s13, v23, 25
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; GCN-NEXT: v_readlane_b32 s14, v23, 26
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; GCN-NEXT: v_readlane_b32 s15, v23, 27
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; GCN-NEXT: v_readlane_b32 s16, v23, 28
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; GCN-NEXT: v_readlane_b32 s17, v23, 29
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; GCN-NEXT: v_readlane_b32 s18, v23, 30
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; GCN-NEXT: v_readlane_b32 s19, v23, 31
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use s[4:19]
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: v_readlane_b32 s4, v23, 32
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; GCN-NEXT: v_readlane_b32 s5, v23, 33
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; GCN-NEXT: v_readlane_b32 s6, v23, 34
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; GCN-NEXT: v_readlane_b32 s7, v23, 35
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; GCN-NEXT: v_readlane_b32 s8, v23, 36
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; GCN-NEXT: v_readlane_b32 s9, v23, 37
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; GCN-NEXT: v_readlane_b32 s10, v23, 38
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; GCN-NEXT: v_readlane_b32 s11, v23, 39
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; GCN-NEXT: v_readlane_b32 s12, v23, 40
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; GCN-NEXT: v_readlane_b32 s13, v23, 41
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; GCN-NEXT: v_readlane_b32 s14, v23, 42
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; GCN-NEXT: v_readlane_b32 s15, v23, 43
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; GCN-NEXT: v_readlane_b32 s16, v23, 44
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; GCN-NEXT: v_readlane_b32 s17, v23, 45
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; GCN-NEXT: v_readlane_b32 s18, v23, 46
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; GCN-NEXT: v_readlane_b32 s19, v23, 47
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use s[4:19]
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: v_readlane_b32 s8, v23, 48
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; GCN-NEXT: v_readlane_b32 s9, v23, 49
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; GCN-NEXT: v_readlane_b32 s10, v23, 50
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; GCN-NEXT: v_readlane_b32 s11, v23, 51
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; GCN-NEXT: v_readlane_b32 s12, v23, 52
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; GCN-NEXT: v_readlane_b32 s13, v23, 53
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; GCN-NEXT: v_readlane_b32 s14, v23, 54
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; GCN-NEXT: v_readlane_b32 s15, v23, 55
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; GCN-NEXT: v_readlane_b32 s16, v23, 56
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; GCN-NEXT: v_readlane_b32 s17, v23, 57
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; GCN-NEXT: v_readlane_b32 s18, v23, 58
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; GCN-NEXT: v_readlane_b32 s19, v23, 59
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; GCN-NEXT: v_readlane_b32 s20, v23, 60
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; GCN-NEXT: v_readlane_b32 s21, v23, 61
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; GCN-NEXT: v_readlane_b32 s22, v23, 62
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; GCN-NEXT: v_readlane_b32 s23, v23, 63
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_readlane_b32 s4, v22, 0
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; GCN-NEXT: v_readlane_b32 s5, v22, 1
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use s[8:23]
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use s[4:5]
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: .LBB0_2: ; %ret
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; GCN-NEXT: s_endpgm
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call void asm sideeffect "", "~{v[0:7]}" () #0
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call void asm sideeffect "", "~{v[8:15]}" () #0
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call void asm sideeffect "", "~{v[16:19]}"() #0
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call void asm sideeffect "", "~{v[20:21]}"() #0
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%wide.sgpr0 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
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%wide.sgpr1 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
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%wide.sgpr2 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
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%wide.sgpr3 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
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%wide.sgpr4 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 %in, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr0) #0
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call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr1) #0
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call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr2) #0
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call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr3) #0
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call void asm sideeffect "; use $0", "s"(<2 x i32> %wide.sgpr4) #0
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br label %ret
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ret:
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind "amdgpu-waves-per-eu"="10,10" }
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