derek.holloway
7502bf64a4
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24 lines
902 B
LLVM
24 lines
902 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
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; rdar://11035895
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; DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) to
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; (i16 load $addr+c*sizeof(i16)). It should have issued an extload instead. i.e.
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; (i32 extload $addr+c*sizeof(i16)
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define void @test_hi_short3(ptr nocapture %srcA, ptr nocapture %dst) nounwind {
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; CHECK-LABEL: test_hi_short3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vmov.u16 r0, d16[2]
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; CHECK-NEXT: vmov.32 d16[0], r0
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; CHECK-NEXT: vuzp.16 d16, d17
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; CHECK-NEXT: vst1.32 {d16[0]}, [r1:32]
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; CHECK-NEXT: bx lr
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entry:
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%0 = load <3 x i16> , ptr %srcA, align 8
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%1 = shufflevector <3 x i16> %0, <3 x i16> undef, <2 x i32> <i32 2, i32 undef>
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store <2 x i16> %1, ptr %dst, align 4
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ret void
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}
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