derek.holloway
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57 lines
1.8 KiB
YAML
57 lines
1.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass=peephole-opt %s -o - -verify-machineinstrs | FileCheck %s
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# The and -> ands transform is sensitive to scheduling; make sure we don't
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# transform cases which aren't legal.
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--- |
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target triple = "armv7-unknown-unknown"
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define i32 @foo_transform(i32 %in) {
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ret i32 undef
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}
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define i32 @foo_notransform(i32 %in) {
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ret i32 undef
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}
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...
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---
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name: foo_transform
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tracksRegLiveness: true
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body: |
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bb.0 (%ir-block.0):
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liveins: $r0
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; CHECK-LABEL: name: foo_transform
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; CHECK: liveins: $r0
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 4, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr
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; CHECK: [[MOVCCi16_:%[0-9]+]]:gpr = MOVCCi16 [[MOVi]], 5, 0 /* CC::eq */, $cpsr
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; CHECK: $r0 = COPY killed [[MOVCCi16_]]
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; CHECK: $r1 = COPY killed [[ANDri]]
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; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
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%1:gpr = COPY $r0
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%2:gpr = MOVi 4, 14, $noreg, $noreg
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%4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg
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TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
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%3:gpr = MOVCCi16 %2, 5, 0, $cpsr
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$r0 = COPY killed %3
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$r1 = COPY killed %4
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BX_RET 14, $noreg, implicit $r0, implicit $r1
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...
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name: foo_notransform
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tracksRegLiveness: true
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body: |
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bb.0 (%ir-block.0):
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liveins: $r0
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%1:gpr = COPY $r0
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%2:gpr = MOVi 4, 14, $noreg, $noreg
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TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
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%3:gpr = MOVCCi16 %2, 5, 0, $cpsr
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%4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg
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$r0 = COPY killed %3
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$r1 = COPY killed %4
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BX_RET 14, $noreg, implicit $r0, implicit $r1
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