derek.holloway
7502bf64a4
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26 lines
1.0 KiB
LLVM
26 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define <4 x i32> @test(<4 x i32> %conv22) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vldi $vr1, -2305
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; CHECK-NEXT: lu12i.w $a0, -524280
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; CHECK-NEXT: ori $a0, $a0, 1
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; CHECK-NEXT: vreplgr2vr.w $vr2, $a0
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; CHECK-NEXT: vmuh.wu $vr2, $vr0, $vr2
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; CHECK-NEXT: vsrli.w $vr2, $vr2, 15
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; CHECK-NEXT: vmsub.w $vr0, $vr2, $vr1
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; CHECK-NEXT: ret
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entry:
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%bc.i = bitcast <16 x i8> zeroinitializer to <8 x i16>
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%vecext.i = extractelement <8 x i16> %bc.i, i64 0
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%not.i1 = xor i16 %vecext.i, -1
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%vecinit24 = insertelement <4 x i16> zeroinitializer, i16 %not.i1, i64 0
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%vecinit27 = shufflevector <4 x i16> %vecinit24, <4 x i16> zeroinitializer, <4 x i32> zeroinitializer
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%conv28 = zext <4 x i16> %vecinit27 to <4 x i32>
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%rem = urem <4 x i32> %conv22, %conv28
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ret <4 x i32> %rem
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}
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