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46 lines
1.9 KiB
LLVM
46 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_35 -verify-machineinstrs | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_35 | %ptxas-verify %}
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; Verify that we correctly emit code for extending ldg/ldu. We do not expose
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; extending variants in the backend, but the ldg/ldu selection code may pick
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; extending loads as candidates. We do want to support this, so make sure we
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; emit the necessary cvt.* instructions to implement the extension and let ptxas
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; emit the real extending loads.
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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define ptx_kernel void @spam(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture %arg1, i64 %arg2, i64 %arg3) #0 {
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; CHECK-LABEL: spam(
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; CHECK: .maxntid 1, 1, 1
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; CHECK-NEXT: {
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; CHECK-NEXT: .reg .b32 %r<2>;
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; CHECK-NEXT: .reg .b64 %rd<9>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0: // %bb
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; CHECK-NEXT: ld.param.b64 %rd1, [spam_param_0];
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; CHECK-NEXT: ld.param.b64 %rd2, [spam_param_3];
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; CHECK-NEXT: shl.b64 %rd3, %rd2, 1;
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; CHECK-NEXT: add.s64 %rd4, %rd1, %rd3;
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; CHECK-NEXT: ld.param.b64 %rd5, [spam_param_1];
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; CHECK-NEXT: ld.global.nc.s16 %r1, [%rd4+16];
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; CHECK-NEXT: mul.wide.s32 %rd6, %r1, %r1;
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; CHECK-NEXT: ld.global.b64 %rd7, [%rd5];
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; CHECK-NEXT: add.s64 %rd8, %rd6, %rd7;
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; CHECK-NEXT: st.global.b64 [%rd5], %rd8;
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; CHECK-NEXT: ret;
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bb:
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%tmp5 = add nsw i64 %arg3, 8
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%tmp6 = getelementptr i16, ptr addrspace(1) %arg, i64 %tmp5
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%tmp7 = load i16, ptr addrspace(1) %tmp6, align 2
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%tmp8 = sext i16 %tmp7 to i64
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%tmp9 = mul nsw i64 %tmp8, %tmp8
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%tmp10 = load i64, ptr addrspace(1) %arg1, align 8
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%tmp11 = add nsw i64 %tmp9, %tmp10
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store i64 %tmp11, ptr addrspace(1) %arg1, align 8
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ret void
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}
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attributes #0 = { norecurse nounwind "polly.skip.fn" "nvvm.maxntid"="1,1,1" }
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