derek.holloway
7502bf64a4
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41 lines
1.8 KiB
LLVM
41 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_80 -mattr=+ptx76 | FileCheck %s
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; RUN: %if ptxas-sm_80 && ptxas-isa-7.6 %{ llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_80 -mattr=+ptx76 | %ptxas-verify -arch=sm_80 %}
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declare i32 @llvm.nvvm.read.ptx.sreg.reserved_smem_offset_begin()
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declare i32 @llvm.nvvm.read.ptx.sreg.reserved_smem_offset_end()
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declare i32 @llvm.nvvm.read.ptx.sreg.reserved_smem_offset_cap()
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declare i32 @llvm.nvvm.read.ptx.sreg.reserved_smem_offset_0()
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declare i32 @llvm.nvvm.read.ptx.sreg.reserved_smem_offset_1()
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define i32 @test() {
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; CHECK-LABEL: test(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<10>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: mov.u32 %r1, %reserved_smem_offset_begin;
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; CHECK-NEXT: mov.u32 %r2, %reserved_smem_offset_end;
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; CHECK-NEXT: mov.u32 %r3, %reserved_smem_offset_cap;
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; CHECK-NEXT: mov.u32 %r4, %reserved_smem_offset_0;
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; CHECK-NEXT: mov.u32 %r5, %reserved_smem_offset_1;
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; CHECK-NEXT: add.s32 %r6, %r1, %r2;
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; CHECK-NEXT: add.s32 %r7, %r6, %r3;
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; CHECK-NEXT: add.s32 %r8, %r7, %r4;
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; CHECK-NEXT: add.s32 %r9, %r8, %r5;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
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; CHECK-NEXT: ret;
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%begin = call i32 @llvm.nvvm.read.ptx.sreg.reserved_smem_offset_begin()
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%end = call i32 @llvm.nvvm.read.ptx.sreg.reserved_smem_offset_end()
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%cap = call i32 @llvm.nvvm.read.ptx.sreg.reserved_smem_offset_cap()
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%offset0 = call i32 @llvm.nvvm.read.ptx.sreg.reserved_smem_offset_0()
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%offset1 = call i32 @llvm.nvvm.read.ptx.sreg.reserved_smem_offset_1()
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%ret0 = add i32 %begin, %end
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%ret1 = add i32 %ret0, %cap
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%ret2 = add i32 %ret1, %offset0
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%ret3 = add i32 %ret2, %offset1
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ret i32 %ret3
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}
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