derek.holloway
7502bf64a4
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367 lines
11 KiB
YAML
367 lines
11 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -mattr=+zfh,+d -run-pass=instruction-select \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -mtriple=riscv64 -mattr=+zfh,+d -run-pass=instruction-select \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: fadd_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_h
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; CHECK-LABEL: name: fadd_f16
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; CHECK: liveins: $f10_h, $f11_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
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; CHECK-NEXT: [[FADD_H:%[0-9]+]]:fpr16 = nofpexcept FADD_H [[COPY]], [[COPY1]], 7
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; CHECK-NEXT: $f10_h = COPY [[FADD_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s16) = COPY $f11_h
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%2:fprb(s16) = G_FADD %0, %1
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$f10_h = COPY %2(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fsub_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_h
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; CHECK-LABEL: name: fsub_f16
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; CHECK: liveins: $f10_h, $f11_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
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; CHECK-NEXT: [[FSUB_H:%[0-9]+]]:fpr16 = nofpexcept FSUB_H [[COPY]], [[COPY1]], 7
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; CHECK-NEXT: $f10_h = COPY [[FSUB_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s16) = COPY $f11_h
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%2:fprb(s16) = G_FSUB %0, %1
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$f10_h = COPY %2(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fmul_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_h
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; CHECK-LABEL: name: fmul_f16
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; CHECK: liveins: $f10_h, $f11_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
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; CHECK-NEXT: [[FMUL_H:%[0-9]+]]:fpr16 = nofpexcept FMUL_H [[COPY]], [[COPY1]], 7
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; CHECK-NEXT: $f10_h = COPY [[FMUL_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s16) = COPY $f11_h
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%2:fprb(s16) = G_FMUL %0, %1
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$f10_h = COPY %2(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fdiv_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_h
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; CHECK-LABEL: name: fdiv_f16
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; CHECK: liveins: $f10_h, $f11_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
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; CHECK-NEXT: [[FDIV_H:%[0-9]+]]:fpr16 = nofpexcept FDIV_H [[COPY]], [[COPY1]], 7
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; CHECK-NEXT: $f10_h = COPY [[FDIV_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s16) = COPY $f11_h
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%2:fprb(s16) = G_FDIV %0, %1
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$f10_h = COPY %2(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fma_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_h, $f12_h
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; CHECK-LABEL: name: fma_f16
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; CHECK: liveins: $f10_h, $f11_h, $f12_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $f12_h
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; CHECK-NEXT: [[FMADD_H:%[0-9]+]]:fpr16 = nofpexcept FMADD_H [[COPY]], [[COPY1]], [[COPY2]], 7
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; CHECK-NEXT: $f10_h = COPY [[FMADD_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s16) = COPY $f11_h
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%2:fprb(s16) = COPY $f12_h
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%3:fprb(s16) = G_FMA %0, %1, %2
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$f10_h = COPY %3(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fneg_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_h, $f12_h
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; CHECK-LABEL: name: fneg_f16
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; CHECK: liveins: $f10_h, $f11_h, $f12_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[FSGNJN_H:%[0-9]+]]:fpr16 = FSGNJN_H [[COPY]], [[COPY]]
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; CHECK-NEXT: $f10_h = COPY [[FSGNJN_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s16) = G_FNEG %0
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$f10_h = COPY %1(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fabs_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_h, $f12_h
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; CHECK-LABEL: name: fabs_f16
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; CHECK: liveins: $f10_h, $f11_h, $f12_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[FSGNJX_H:%[0-9]+]]:fpr16 = FSGNJX_H [[COPY]], [[COPY]]
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; CHECK-NEXT: $f10_h = COPY [[FSGNJX_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s16) = G_FABS %0
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$f10_h = COPY %1(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fsqrt_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_h, $f12_h
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; CHECK-LABEL: name: fsqrt_f16
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; CHECK: liveins: $f10_h, $f11_h, $f12_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[FSQRT_H:%[0-9]+]]:fpr16 = nofpexcept FSQRT_H [[COPY]], 7
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; CHECK-NEXT: $f10_h = COPY [[FSQRT_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s16) = G_FSQRT %0
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$f10_h = COPY %1(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fmaxnum_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_h
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; CHECK-LABEL: name: fmaxnum_f16
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; CHECK: liveins: $f10_h, $f11_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
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; CHECK-NEXT: [[FMAX_H:%[0-9]+]]:fpr16 = nofpexcept FMAX_H [[COPY]], [[COPY1]]
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; CHECK-NEXT: $f10_h = COPY [[FMAX_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s16) = COPY $f11_h
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%2:fprb(s16) = G_FMAXNUM %0, %1
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$f10_h = COPY %2(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fminnum_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_h
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; CHECK-LABEL: name: fminnum_f16
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; CHECK: liveins: $f10_h, $f11_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
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; CHECK-NEXT: [[FMIN_H:%[0-9]+]]:fpr16 = nofpexcept FMIN_H [[COPY]], [[COPY1]]
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; CHECK-NEXT: $f10_h = COPY [[FMIN_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s16) = COPY $f11_h
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%2:fprb(s16) = G_FMINNUM %0, %1
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$f10_h = COPY %2(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fcopysign_f16_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_h
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; CHECK-LABEL: name: fcopysign_f16_f16
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; CHECK: liveins: $f10_h, $f11_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
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; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[COPY1]]
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; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s16) = COPY $f11_h
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%2:fprb(s16) = G_FCOPYSIGN %0, %1
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$f10_h = COPY %2(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fcopysign_f16_f32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_f
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; CHECK-LABEL: name: fcopysign_f16_f32
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; CHECK: liveins: $f10_h, $f11_f
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
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; CHECK-NEXT: [[FCVT_H_S:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_S [[COPY1]], 7
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; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[FCVT_H_S]]
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; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s32) = COPY $f11_f
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%2:fprb(s16) = G_FCOPYSIGN %0, %1
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$f10_h = COPY %2(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fcopysign_f32_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_f, $f11_h
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; CHECK-LABEL: name: fcopysign_f32_f16
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; CHECK: liveins: $f10_f, $f11_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
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; CHECK-NEXT: [[FCVT_S_H:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_H [[COPY1]], 0
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; CHECK-NEXT: [[FSGNJ_S:%[0-9]+]]:fpr32 = FSGNJ_S [[COPY]], [[FCVT_S_H]]
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; CHECK-NEXT: $f10_f = COPY [[FSGNJ_S]]
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; CHECK-NEXT: PseudoRET implicit $f10_f
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%0:fprb(s32) = COPY $f10_f
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%1:fprb(s16) = COPY $f11_h
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%2:fprb(s32) = G_FCOPYSIGN %0, %1
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$f10_f = COPY %2(s32)
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PseudoRET implicit $f10_f
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...
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---
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name: fcopysign_f16_f64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_h, $f11_d
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; CHECK-LABEL: name: fcopysign_f16_f64
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; CHECK: liveins: $f10_h, $f11_d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
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; CHECK-NEXT: [[FCVT_H_D:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_D [[COPY1]], 7
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; CHECK-NEXT: [[FSGNJ_H:%[0-9]+]]:fpr16 = FSGNJ_H [[COPY]], [[FCVT_H_D]]
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; CHECK-NEXT: $f10_h = COPY [[FSGNJ_H]]
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; CHECK-NEXT: PseudoRET implicit $f10_h
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%0:fprb(s16) = COPY $f10_h
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%1:fprb(s64) = COPY $f11_d
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%2:fprb(s16) = G_FCOPYSIGN %0, %1
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$f10_h = COPY %2(s16)
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PseudoRET implicit $f10_h
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...
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---
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name: fcopysign_f64_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_d, $f11_h
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; CHECK-LABEL: name: fcopysign_f64_f16
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; CHECK: liveins: $f10_d, $f11_h
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
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; CHECK-NEXT: [[FCVT_D_H:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_H [[COPY1]], 0
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; CHECK-NEXT: [[FSGNJ_D:%[0-9]+]]:fpr64 = FSGNJ_D [[COPY]], [[FCVT_D_H]]
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; CHECK-NEXT: $f10_d = COPY [[FSGNJ_D]]
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; CHECK-NEXT: PseudoRET implicit $f10_d
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%0:fprb(s64) = COPY $f10_d
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%1:fprb(s16) = COPY $f11_h
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%2:fprb(s64) = G_FCOPYSIGN %0, %1
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$f10_d = COPY %2(s64)
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PseudoRET implicit $f10_d
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...
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