derek.holloway
7502bf64a4
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85 lines
4.1 KiB
LLVM
85 lines
4.1 KiB
LLVM
; RUN: llc -mtriple=riscv32 -O0 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
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; RUN: grep -v "Verify generated machine code" | \
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; RUN: FileCheck %s --check-prefixes=CHECK
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; RUN: llc -mtriple=riscv64 -O0 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
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; RUN: grep -v "Verify generated machine code" | \
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; RUN: FileCheck %s --check-prefixes=CHECK
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; REQUIRES: asserts
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; CHECK-LABEL: Pass Arguments:
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; CHECK-NEXT: Target Library Information
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; CHECK-NEXT: Runtime Library Function Analysis
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; CHECK-NEXT: Target Pass Configuration
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; CHECK-NEXT: Machine Module Information
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; CHECK-NEXT: Target Transform Information
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; CHECK-NEXT: Library Function Lowering Analysis
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; CHECK-NEXT: Create Garbage Collector Module Metadata
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; CHECK-NEXT: Assumption Cache Tracker
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; CHECK-NEXT: Profile summary info
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; CHECK-NEXT: Machine Branch Probability Analysis
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; CHECK-NEXT: ModulePass Manager
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; CHECK-NEXT: Pre-ISel Intrinsic Lowering
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Expand IR instructions
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; CHECK-NEXT: Expand Atomic instructions
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; CHECK-NEXT: RISC-V Zacas ABI fix
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; CHECK-NEXT: Module Verifier
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; CHECK-NEXT: Lower Garbage Collection Instructions
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; CHECK-NEXT: Shadow Stack GC Lowering
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; CHECK-NEXT: Remove unreachable blocks from the CFG
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; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining)
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; CHECK-NEXT: Scalarize Masked Memory Intrinsics
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; CHECK-NEXT: Expand reduction intrinsics
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; CHECK-NEXT: Exception handling preparation
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; CHECK-NEXT: Prepare inline asm insts
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; CHECK-NEXT: Safe Stack instrumentation pass
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; CHECK-NEXT: Insert stack protectors
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; CHECK-NEXT: Module Verifier
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; CHECK-NEXT: Assignment Tracking Analysis
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; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
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; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
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; CHECK-NEXT: Local Stack Slot Allocation
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; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
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; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
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; CHECK-NEXT: RISC-V Insert Write VXRM Pass
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; CHECK-NEXT: RISC-V Landing Pad Setup
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; CHECK-NEXT: RISC-V VMV0 Elimination
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; CHECK-NEXT: Init Undef Pass
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; CHECK-NEXT: Eliminate PHI nodes for register allocation
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; CHECK-NEXT: Two-Address instruction pass
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; CHECK-NEXT: Fast Register Allocator
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; CHECK-NEXT: RISC-V Insert VSETVLI pass
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; CHECK-NEXT: Fast Register Allocator
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; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
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; CHECK-NEXT: Fixup Statepoint Caller Saved
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
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; CHECK-NEXT: Post-RA pseudo instruction expansion pass
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; CHECK-NEXT: RISC-V post-regalloc pseudo instruction expansion pass
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; CHECK-NEXT: Insert KCFI indirect call checks
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; CHECK-NEXT: Analyze Machine Code For Garbage Collection
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; CHECK-NEXT: Insert fentry calls
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; CHECK-NEXT: Insert XRay ops
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; CHECK-NEXT: Implement the 'patchable-function' attribute
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; CHECK-NEXT: RISC-V Indirect Branch Tracking
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; CHECK-NEXT: Branch relaxation pass
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; CHECK-NEXT: RISC-V Make Compressible
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; CHECK-NEXT: Contiguously Lay Out Funclets
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; CHECK-NEXT: Remove Loads Into Fake Uses
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; CHECK-NEXT: StackMap Liveness Analysis
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; CHECK-NEXT: Live DEBUG_VALUE analysis
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; CHECK-NEXT: Machine Sanitizer Binary Metadata
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; CHECK-NEXT: Insert CFI remember/restore state instructions
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Stack Frame Layout Analysis
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; CHECK-NEXT: RISC-V pseudo instruction expansion pass
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; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
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; CHECK-NEXT: Unpack machine instruction bundles
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: RISC-V Assembly Printer
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; CHECK-NEXT: Free MachineFunction
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