derek.holloway
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79 lines
2.5 KiB
LLVM
79 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -mattr=+d -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IFD-LE %s
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; RUN: llc -mtriple=riscv32be -target-abi=ilp32 -mattr=+d -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IFD-BE %s
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; Test operations that involve SplitF64/BuildPairF64 on RV32 with D extension
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; but soft-float ABI. This configuration triggers the special handling for
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; big-endian.
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define double @fneg(double %a) nounwind {
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; RV32IFD-LE-LABEL: fneg:
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; RV32IFD-LE: # %bb.0:
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; RV32IFD-LE-NEXT: lui a2, 524288
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; RV32IFD-LE-NEXT: xor a1, a1, a2
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; RV32IFD-LE-NEXT: ret
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;
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; RV32IFD-BE-LABEL: fneg:
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; RV32IFD-BE: # %bb.0:
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; RV32IFD-BE-NEXT: lui a2, 524288
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; RV32IFD-BE-NEXT: xor a0, a0, a2
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; RV32IFD-BE-NEXT: ret
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%1 = fneg double %a
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ret double %1
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}
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define double @fabs(double %a) nounwind {
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; RV32IFD-LE-LABEL: fabs:
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; RV32IFD-LE: # %bb.0:
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; RV32IFD-LE-NEXT: slli a1, a1, 1
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; RV32IFD-LE-NEXT: srli a1, a1, 1
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; RV32IFD-LE-NEXT: ret
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;
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; RV32IFD-BE-LABEL: fabs:
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; RV32IFD-BE: # %bb.0:
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; RV32IFD-BE-NEXT: slli a0, a0, 1
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; RV32IFD-BE-NEXT: srli a0, a0, 1
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; RV32IFD-BE-NEXT: ret
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%1 = call double @llvm.fabs.f64(double %a)
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ret double %1
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}
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define double @fcopysign(double %a, double %b) nounwind {
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; RV32IFD-LE-LABEL: fcopysign:
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; RV32IFD-LE: # %bb.0:
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; RV32IFD-LE-NEXT: addi sp, sp, -16
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; RV32IFD-LE-NEXT: sw a2, 8(sp)
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; RV32IFD-LE-NEXT: sw a3, 12(sp)
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; RV32IFD-LE-NEXT: fld fa5, 8(sp)
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; RV32IFD-LE-NEXT: sw a0, 8(sp)
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; RV32IFD-LE-NEXT: sw a1, 12(sp)
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; RV32IFD-LE-NEXT: fld fa4, 8(sp)
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; RV32IFD-LE-NEXT: fsgnj.d fa5, fa4, fa5
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; RV32IFD-LE-NEXT: fsd fa5, 8(sp)
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; RV32IFD-LE-NEXT: lw a0, 8(sp)
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; RV32IFD-LE-NEXT: lw a1, 12(sp)
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; RV32IFD-LE-NEXT: addi sp, sp, 16
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; RV32IFD-LE-NEXT: ret
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;
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; RV32IFD-BE-LABEL: fcopysign:
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; RV32IFD-BE: # %bb.0:
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; RV32IFD-BE-NEXT: addi sp, sp, -16
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; RV32IFD-BE-NEXT: sw a2, 8(sp)
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; RV32IFD-BE-NEXT: sw a3, 12(sp)
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; RV32IFD-BE-NEXT: fld fa5, 8(sp)
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; RV32IFD-BE-NEXT: sw a0, 8(sp)
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; RV32IFD-BE-NEXT: sw a1, 12(sp)
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; RV32IFD-BE-NEXT: fld fa4, 8(sp)
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; RV32IFD-BE-NEXT: fsgnj.d fa5, fa4, fa5
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; RV32IFD-BE-NEXT: fsd fa5, 8(sp)
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; RV32IFD-BE-NEXT: lw a0, 8(sp)
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; RV32IFD-BE-NEXT: lw a1, 12(sp)
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; RV32IFD-BE-NEXT: addi sp, sp, 16
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; RV32IFD-BE-NEXT: ret
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%1 = call double @llvm.copysign.f64(double %a, double %b)
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ret double %1
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}
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declare double @llvm.fabs.f64(double)
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declare double @llvm.copysign.f64(double, double)
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