derek.holloway
7502bf64a4
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167 lines
6.8 KiB
YAML
167 lines
6.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -mattr=+reserve-x6 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \
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# RUN: -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK-X6-RESERVED %s
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# RUN: llc -mtriple=riscv32 -mattr=+reserve-x6,+reserve-x7 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \
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# RUN: -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK-X6-X7-RESERVED %s
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--- |
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define i32 @outline_x5_live_reserved_0(i32 %a, i32 %b) { ret i32 0 }
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define i32 @outline_x5_live_reserved_1(i32 %a, i32 %b) { ret i32 0 }
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define i32 @outline_x5_live_reserved_2(i32 %a, i32 %b) { ret i32 0 }
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...
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---
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name: outline_x5_live_reserved_0
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tracksRegLiveness: true
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body: |
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; CHECK-X6-RESERVED-LABEL: name: outline_x5_live_reserved_0
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; CHECK-X6-RESERVED: bb.0:
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; CHECK-X6-RESERVED-NEXT: liveins: $x10, $x11, $x5
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; CHECK-X6-RESERVED-NEXT: {{ $}}
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; CHECK-X6-RESERVED-NEXT: $x7 = ADDI $x5, 0
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; CHECK-X6-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x7, implicit $x10, implicit $x11
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; CHECK-X6-RESERVED-NEXT: $x5 = ADDI $x7, 0
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; CHECK-X6-RESERVED-NEXT: PseudoBR %bb.1
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; CHECK-X6-RESERVED-NEXT: {{ $}}
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; CHECK-X6-RESERVED-NEXT: bb.1:
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; CHECK-X6-RESERVED-NEXT: liveins: $x5, $x14
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; CHECK-X6-RESERVED-NEXT: {{ $}}
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; CHECK-X6-RESERVED-NEXT: $x10 = ADD $x14, $x5
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; CHECK-X6-RESERVED-NEXT: PseudoRET implicit $x10
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;
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; CHECK-X6-X7-RESERVED-LABEL: name: outline_x5_live_reserved_0
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; CHECK-X6-X7-RESERVED: bb.0:
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; CHECK-X6-X7-RESERVED-NEXT: liveins: $x10, $x11, $x5
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; CHECK-X6-X7-RESERVED-NEXT: {{ $}}
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; CHECK-X6-X7-RESERVED-NEXT: $x28 = ADDI $x5, 0
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; CHECK-X6-X7-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28
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; CHECK-X6-X7-RESERVED-NEXT: $x5 = ADDI $x28, 0
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; CHECK-X6-X7-RESERVED-NEXT: PseudoBR %bb.1
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; CHECK-X6-X7-RESERVED-NEXT: {{ $}}
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; CHECK-X6-X7-RESERVED-NEXT: bb.1:
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; CHECK-X6-X7-RESERVED-NEXT: liveins: $x5, $x14
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; CHECK-X6-X7-RESERVED-NEXT: {{ $}}
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; CHECK-X6-X7-RESERVED-NEXT: $x10 = ADD $x14, $x5
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; CHECK-X6-X7-RESERVED-NEXT: PseudoRET implicit $x10
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bb.0:
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liveins: $x10, $x11, $x5
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$x11 = ANDI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x14 = SUB $x10, $x11
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$x11 = ANDI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x14 = SUB $x10, $x11
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PseudoBR %bb.1
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bb.1:
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liveins: $x5, $x14
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$x10 = ADD $x14, $x5
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PseudoRET implicit $x10
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...
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---
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name: outline_x5_live_reserved_1
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tracksRegLiveness: true
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body: |
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; CHECK-X6-RESERVED-LABEL: name: outline_x5_live_reserved_1
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; CHECK-X6-RESERVED: bb.0:
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; CHECK-X6-RESERVED-NEXT: liveins: $x10, $x11, $x5
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; CHECK-X6-RESERVED-NEXT: {{ $}}
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; CHECK-X6-RESERVED-NEXT: $x7 = ADDI $x5, 0
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; CHECK-X6-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x7, implicit $x10, implicit $x11
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; CHECK-X6-RESERVED-NEXT: $x5 = ADDI $x7, 0
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; CHECK-X6-RESERVED-NEXT: PseudoBR %bb.1
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; CHECK-X6-RESERVED-NEXT: {{ $}}
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; CHECK-X6-RESERVED-NEXT: bb.1:
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; CHECK-X6-RESERVED-NEXT: liveins: $x5, $x14
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; CHECK-X6-RESERVED-NEXT: {{ $}}
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; CHECK-X6-RESERVED-NEXT: $x10 = ADD $x14, $x5
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; CHECK-X6-RESERVED-NEXT: PseudoRET implicit $x10
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;
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; CHECK-X6-X7-RESERVED-LABEL: name: outline_x5_live_reserved_1
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; CHECK-X6-X7-RESERVED: bb.0:
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; CHECK-X6-X7-RESERVED-NEXT: liveins: $x10, $x11, $x5
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; CHECK-X6-X7-RESERVED-NEXT: {{ $}}
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; CHECK-X6-X7-RESERVED-NEXT: $x28 = ADDI $x5, 0
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; CHECK-X6-X7-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28
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; CHECK-X6-X7-RESERVED-NEXT: $x5 = ADDI $x28, 0
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; CHECK-X6-X7-RESERVED-NEXT: PseudoBR %bb.1
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; CHECK-X6-X7-RESERVED-NEXT: {{ $}}
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; CHECK-X6-X7-RESERVED-NEXT: bb.1:
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; CHECK-X6-X7-RESERVED-NEXT: liveins: $x5, $x14
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; CHECK-X6-X7-RESERVED-NEXT: {{ $}}
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; CHECK-X6-X7-RESERVED-NEXT: $x10 = ADD $x14, $x5
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; CHECK-X6-X7-RESERVED-NEXT: PseudoRET implicit $x10
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bb.0:
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liveins: $x10, $x11, $x5
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$x11 = ANDI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x14 = SUB $x10, $x11
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$x11 = ANDI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x14 = SUB $x10, $x11
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PseudoBR %bb.1
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bb.1:
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liveins: $x5, $x14
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$x10 = ADD $x14, $x5
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PseudoRET implicit $x10
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...
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---
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name: outline_x5_live_reserved_2
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tracksRegLiveness: true
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body: |
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; CHECK-X6-RESERVED-LABEL: name: outline_x5_live_reserved_2
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; CHECK-X6-RESERVED: bb.0:
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; CHECK-X6-RESERVED-NEXT: liveins: $x10, $x11, $x5
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; CHECK-X6-RESERVED-NEXT: {{ $}}
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; CHECK-X6-RESERVED-NEXT: $x7 = ADDI $x5, 0
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; CHECK-X6-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x7, implicit $x10, implicit $x11
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; CHECK-X6-RESERVED-NEXT: $x5 = ADDI $x7, 0
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; CHECK-X6-RESERVED-NEXT: PseudoBR %bb.1
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; CHECK-X6-RESERVED-NEXT: {{ $}}
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; CHECK-X6-RESERVED-NEXT: bb.1:
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; CHECK-X6-RESERVED-NEXT: liveins: $x5, $x14
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; CHECK-X6-RESERVED-NEXT: {{ $}}
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; CHECK-X6-RESERVED-NEXT: $x10 = ADD $x14, $x5
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; CHECK-X6-RESERVED-NEXT: PseudoRET implicit $x10
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;
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; CHECK-X6-X7-RESERVED-LABEL: name: outline_x5_live_reserved_2
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; CHECK-X6-X7-RESERVED: bb.0:
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; CHECK-X6-X7-RESERVED-NEXT: liveins: $x10, $x11, $x5
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; CHECK-X6-X7-RESERVED-NEXT: {{ $}}
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; CHECK-X6-X7-RESERVED-NEXT: $x28 = ADDI $x5, 0
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; CHECK-X6-X7-RESERVED-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x10, implicit $x11, implicit $x28
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; CHECK-X6-X7-RESERVED-NEXT: $x5 = ADDI $x28, 0
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; CHECK-X6-X7-RESERVED-NEXT: PseudoBR %bb.1
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; CHECK-X6-X7-RESERVED-NEXT: {{ $}}
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; CHECK-X6-X7-RESERVED-NEXT: bb.1:
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; CHECK-X6-X7-RESERVED-NEXT: liveins: $x5, $x14
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; CHECK-X6-X7-RESERVED-NEXT: {{ $}}
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; CHECK-X6-X7-RESERVED-NEXT: $x10 = ADD $x14, $x5
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; CHECK-X6-X7-RESERVED-NEXT: PseudoRET implicit $x10
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bb.0:
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liveins: $x10, $x11, $x5
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$x11 = ANDI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x14 = SUB $x10, $x11
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$x11 = ANDI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x14 = SUB $x10, $x11
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PseudoBR %bb.1
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bb.1:
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liveins: $x5, $x14
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$x10 = ADD $x14, $x5
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PseudoRET implicit $x10
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...
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