derek.holloway
7502bf64a4
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205 lines
6.0 KiB
LLVM
205 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -mtriple=riscv32 -mattr=+v < %s | FileCheck %s -check-prefix=RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s -check-prefix=RV64
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; WITH VSCALE RANGE
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define i32 @ctz_nxv4i32(<vscale x 4 x i32> %a) #0 {
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; RV32-LABEL: ctz_nxv4i32:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; RV32-NEXT: vmsne.vi v10, v8, 0
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; RV32-NEXT: vfirst.m a0, v10
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; RV32-NEXT: bgez a0, .LBB0_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: srli a0, a0, 1
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; RV32-NEXT: .LBB0_2:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: ctz_nxv4i32:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; RV64-NEXT: vmsne.vi v10, v8, 0
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; RV64-NEXT: vfirst.m a0, v10
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; RV64-NEXT: bgez a0, .LBB0_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: srli a0, a0, 1
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; RV64-NEXT: .LBB0_2:
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; RV64-NEXT: ret
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%res = call i32 @llvm.experimental.cttz.elts.i32.nxv4i32(<vscale x 4 x i32> %a, i1 0)
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ret i32 %res
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}
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; NO VSCALE RANGE
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define i64 @ctz_nxv8i1_no_range(<vscale x 8 x i16> %a) {
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; RV32-LABEL: ctz_nxv8i1_no_range:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; RV32-NEXT: vmsne.vi v10, v8, 0
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; RV32-NEXT: vfirst.m a0, v10
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; RV32-NEXT: bgez a0, .LBB1_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: .LBB1_2:
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: ctz_nxv8i1_no_range:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; RV64-NEXT: vmsne.vi v10, v8, 0
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; RV64-NEXT: vfirst.m a0, v10
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; RV64-NEXT: bgez a0, .LBB1_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: .LBB1_2:
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; RV64-NEXT: ret
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%res = call i64 @llvm.experimental.cttz.elts.i64.nxv8i16(<vscale x 8 x i16> %a, i1 0)
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ret i64 %res
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}
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define i32 @ctz_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; RV32-LABEL: ctz_nxv16i1:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; RV32-NEXT: vfirst.m a0, v8
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; RV32-NEXT: bgez a0, .LBB2_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: csrr a0, vlenb
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; RV32-NEXT: slli a0, a0, 1
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; RV32-NEXT: .LBB2_2:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: ctz_nxv16i1:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; RV64-NEXT: vfirst.m a0, v8
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; RV64-NEXT: bgez a0, .LBB2_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: csrr a0, vlenb
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; RV64-NEXT: slli a0, a0, 1
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; RV64-NEXT: .LBB2_2:
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; RV64-NEXT: ret
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%res = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1(<vscale x 16 x i1> %a, i1 0)
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ret i32 %res
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}
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define i64 @i64_ctz_nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; RV32-LABEL: i64_ctz_nxv16i1:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; RV32-NEXT: vfirst.m a0, v8
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: i64_ctz_nxv16i1:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; RV64-NEXT: vfirst.m a0, v8
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; RV64-NEXT: ret
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%res = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1(<vscale x 16 x i1> %a, i1 1)
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ret i64 %res
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}
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define i64 @i64_ctz_nxv16i1_range(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) vscale_range(2, 1024) {
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; RV32-LABEL: i64_ctz_nxv16i1_range:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; RV32-NEXT: vfirst.m a0, v8
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: i64_ctz_nxv16i1_range:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; RV64-NEXT: vfirst.m a0, v8
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; RV64-NEXT: ret
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%res = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1(<vscale x 16 x i1> %a, i1 1)
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ret i64 %res
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}
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define i32 @ctz_nxv16i1_poison(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; RV32-LABEL: ctz_nxv16i1_poison:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; RV32-NEXT: vfirst.m a0, v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: ctz_nxv16i1_poison:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; RV64-NEXT: vfirst.m a0, v8
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; RV64-NEXT: ret
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%res = call i32 @llvm.experimental.cttz.elts.i32.nxv16i1(<vscale x 16 x i1> %a, i1 1)
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ret i32 %res
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}
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define i32 @ctz_v16i1(<16 x i1> %pg, <16 x i1> %a) {
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; RV32-LABEL: ctz_v16i1:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; RV32-NEXT: vfirst.m a0, v8
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; RV32-NEXT: bgez a0, .LBB6_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: li a0, 16
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; RV32-NEXT: .LBB6_2:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: ctz_v16i1:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; RV64-NEXT: vfirst.m a0, v8
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; RV64-NEXT: bgez a0, .LBB6_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: li a0, 16
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; RV64-NEXT: .LBB6_2:
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; RV64-NEXT: ret
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%res = call i32 @llvm.experimental.cttz.elts.i32.v16i1(<16 x i1> %a, i1 0)
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ret i32 %res
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}
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define i32 @ctz_v16i1_poison(<16 x i1> %pg, <16 x i1> %a) {
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; RV32-LABEL: ctz_v16i1_poison:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; RV32-NEXT: vfirst.m a0, v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: ctz_v16i1_poison:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; RV64-NEXT: vfirst.m a0, v8
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; RV64-NEXT: ret
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%res = call i32 @llvm.experimental.cttz.elts.i32.v16i1(<16 x i1> %a, i1 1)
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ret i32 %res
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}
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define i16 @ctz_v8i1_i16_ret(<8 x i1> %a) {
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; RV32-LABEL: ctz_v8i1_i16_ret:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; RV32-NEXT: vfirst.m a0, v0
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; RV32-NEXT: bgez a0, .LBB8_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: li a0, 8
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; RV32-NEXT: .LBB8_2:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: ctz_v8i1_i16_ret:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; RV64-NEXT: vfirst.m a0, v0
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; RV64-NEXT: bgez a0, .LBB8_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: li a0, 8
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; RV64-NEXT: .LBB8_2:
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; RV64-NEXT: ret
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%res = call i16 @llvm.experimental.cttz.elts.i16.v8i1(<8 x i1> %a, i1 0)
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ret i16 %res
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}
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attributes #0 = { vscale_range(2,1024) }
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