derek.holloway
7502bf64a4
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157 lines
5.5 KiB
LLVM
157 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32I-M
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64I-M
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+short-forward-branch-ialu | \
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; RUN: FileCheck %s --check-prefixes=RV32I-SFB-M
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+short-forward-branch-ialu | \
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; RUN: FileCheck %s --check-prefixes=RV64I-SFB-M
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+short-forward-branch-imul | \
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; RUN: FileCheck %s --check-prefixes=RV32I-SFBIMul-M
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+short-forward-branch-imul | \
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; RUN: FileCheck %s --check-prefixes=RV64I-SFBIMul-M
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define i32 @select_example_mul_i32(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
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; RV32I-M-LABEL: select_example_mul_i32:
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; RV32I-M: # %bb.0: # %entry
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; RV32I-M-NEXT: beqz a2, .LBB0_2
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; RV32I-M-NEXT: # %bb.1:
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; RV32I-M-NEXT: mul a1, a0, a3
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; RV32I-M-NEXT: .LBB0_2: # %entry
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; RV32I-M-NEXT: mv a0, a1
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; RV32I-M-NEXT: ret
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;
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; RV64I-M-LABEL: select_example_mul_i32:
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; RV64I-M: # %bb.0: # %entry
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; RV64I-M-NEXT: beqz a2, .LBB0_2
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; RV64I-M-NEXT: # %bb.1:
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; RV64I-M-NEXT: mulw a1, a0, a3
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; RV64I-M-NEXT: .LBB0_2: # %entry
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; RV64I-M-NEXT: mv a0, a1
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; RV64I-M-NEXT: ret
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;
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; RV32I-SFB-M-LABEL: select_example_mul_i32:
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; RV32I-SFB-M: # %bb.0: # %entry
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; RV32I-SFB-M-NEXT: mul a0, a0, a3
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; RV32I-SFB-M-NEXT: bnez a2, .LBB0_2
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; RV32I-SFB-M-NEXT: # %bb.1: # %entry
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; RV32I-SFB-M-NEXT: mv a0, a1
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; RV32I-SFB-M-NEXT: .LBB0_2: # %entry
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; RV32I-SFB-M-NEXT: ret
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;
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; RV64I-SFB-M-LABEL: select_example_mul_i32:
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; RV64I-SFB-M: # %bb.0: # %entry
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; RV64I-SFB-M-NEXT: mulw a0, a0, a3
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; RV64I-SFB-M-NEXT: bnez a2, .LBB0_2
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; RV64I-SFB-M-NEXT: # %bb.1: # %entry
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; RV64I-SFB-M-NEXT: mv a0, a1
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; RV64I-SFB-M-NEXT: .LBB0_2: # %entry
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; RV64I-SFB-M-NEXT: ret
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;
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; RV32I-SFBIMul-M-LABEL: select_example_mul_i32:
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; RV32I-SFBIMul-M: # %bb.0: # %entry
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; RV32I-SFBIMul-M-NEXT: beqz a2, .LBB0_2
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; RV32I-SFBIMul-M-NEXT: # %bb.1: # %entry
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; RV32I-SFBIMul-M-NEXT: mul a1, a0, a3
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; RV32I-SFBIMul-M-NEXT: .LBB0_2: # %entry
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; RV32I-SFBIMul-M-NEXT: mv a0, a1
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; RV32I-SFBIMul-M-NEXT: ret
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;
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; RV64I-SFBIMul-M-LABEL: select_example_mul_i32:
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; RV64I-SFBIMul-M: # %bb.0: # %entry
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; RV64I-SFBIMul-M-NEXT: mulw a0, a0, a3
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; RV64I-SFBIMul-M-NEXT: bnez a2, .LBB0_2
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; RV64I-SFBIMul-M-NEXT: # %bb.1: # %entry
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; RV64I-SFBIMul-M-NEXT: mv a0, a1
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; RV64I-SFBIMul-M-NEXT: .LBB0_2: # %entry
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; RV64I-SFBIMul-M-NEXT: ret
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entry:
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%res = mul i32 %a, %y
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%sel = select i1 %x, i32 %res, i32 %b
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ret i32 %sel
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}
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define i64 @select_example_mul_i64(i64 %a, i64 %b, i1 zeroext %x, i64 %y) {
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; RV32I-M-LABEL: select_example_mul_i64:
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; RV32I-M: # %bb.0: # %entry
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; RV32I-M-NEXT: beqz a4, .LBB1_2
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; RV32I-M-NEXT: # %bb.1:
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; RV32I-M-NEXT: mul a2, a0, a6
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; RV32I-M-NEXT: mulhu a3, a0, a5
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; RV32I-M-NEXT: mul a1, a1, a5
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; RV32I-M-NEXT: add a2, a3, a2
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; RV32I-M-NEXT: add a3, a2, a1
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; RV32I-M-NEXT: mul a2, a0, a5
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; RV32I-M-NEXT: .LBB1_2: # %entry
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; RV32I-M-NEXT: mv a0, a2
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; RV32I-M-NEXT: mv a1, a3
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; RV32I-M-NEXT: ret
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;
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; RV64I-M-LABEL: select_example_mul_i64:
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; RV64I-M: # %bb.0: # %entry
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; RV64I-M-NEXT: beqz a2, .LBB1_2
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; RV64I-M-NEXT: # %bb.1:
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; RV64I-M-NEXT: mul a1, a0, a3
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; RV64I-M-NEXT: .LBB1_2: # %entry
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; RV64I-M-NEXT: mv a0, a1
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; RV64I-M-NEXT: ret
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;
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; RV32I-SFB-M-LABEL: select_example_mul_i64:
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; RV32I-SFB-M: # %bb.0: # %entry
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; RV32I-SFB-M-NEXT: mul a6, a0, a6
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; RV32I-SFB-M-NEXT: mulhu a7, a0, a5
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; RV32I-SFB-M-NEXT: mul a1, a1, a5
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; RV32I-SFB-M-NEXT: mul a0, a0, a5
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; RV32I-SFB-M-NEXT: add a6, a7, a6
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; RV32I-SFB-M-NEXT: beqz a4, .LBB1_2
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; RV32I-SFB-M-NEXT: # %bb.1: # %entry
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; RV32I-SFB-M-NEXT: add a3, a6, a1
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; RV32I-SFB-M-NEXT: .LBB1_2: # %entry
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; RV32I-SFB-M-NEXT: bnez a4, .LBB1_4
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; RV32I-SFB-M-NEXT: # %bb.3: # %entry
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; RV32I-SFB-M-NEXT: mv a0, a2
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; RV32I-SFB-M-NEXT: .LBB1_4: # %entry
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; RV32I-SFB-M-NEXT: mv a1, a3
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; RV32I-SFB-M-NEXT: ret
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;
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; RV64I-SFB-M-LABEL: select_example_mul_i64:
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; RV64I-SFB-M: # %bb.0: # %entry
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; RV64I-SFB-M-NEXT: mul a0, a0, a3
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; RV64I-SFB-M-NEXT: bnez a2, .LBB1_2
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; RV64I-SFB-M-NEXT: # %bb.1: # %entry
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; RV64I-SFB-M-NEXT: mv a0, a1
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; RV64I-SFB-M-NEXT: .LBB1_2: # %entry
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; RV64I-SFB-M-NEXT: ret
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;
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; RV32I-SFBIMul-M-LABEL: select_example_mul_i64:
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; RV32I-SFBIMul-M: # %bb.0: # %entry
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; RV32I-SFBIMul-M-NEXT: mul a6, a0, a6
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; RV32I-SFBIMul-M-NEXT: mulhu a7, a0, a5
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; RV32I-SFBIMul-M-NEXT: mul a1, a1, a5
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; RV32I-SFBIMul-M-NEXT: add a6, a7, a6
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; RV32I-SFBIMul-M-NEXT: beqz a4, .LBB1_2
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; RV32I-SFBIMul-M-NEXT: # %bb.1: # %entry
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; RV32I-SFBIMul-M-NEXT: add a3, a6, a1
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; RV32I-SFBIMul-M-NEXT: .LBB1_2: # %entry
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; RV32I-SFBIMul-M-NEXT: beqz a4, .LBB1_4
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; RV32I-SFBIMul-M-NEXT: # %bb.3: # %entry
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; RV32I-SFBIMul-M-NEXT: mul a2, a0, a5
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; RV32I-SFBIMul-M-NEXT: .LBB1_4: # %entry
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; RV32I-SFBIMul-M-NEXT: mv a0, a2
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; RV32I-SFBIMul-M-NEXT: mv a1, a3
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; RV32I-SFBIMul-M-NEXT: ret
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;
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; RV64I-SFBIMul-M-LABEL: select_example_mul_i64:
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; RV64I-SFBIMul-M: # %bb.0: # %entry
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; RV64I-SFBIMul-M-NEXT: beqz a2, .LBB1_2
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; RV64I-SFBIMul-M-NEXT: # %bb.1: # %entry
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; RV64I-SFBIMul-M-NEXT: mul a1, a0, a3
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; RV64I-SFBIMul-M-NEXT: .LBB1_2: # %entry
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; RV64I-SFBIMul-M-NEXT: mv a0, a1
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; RV64I-SFBIMul-M-NEXT: ret
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entry:
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%res = mul i64 %a, %y
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%sel = select i1 %x, i64 %res, i64 %b
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ret i64 %sel
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}
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