derek.holloway
7502bf64a4
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214 lines
8.9 KiB
YAML
214 lines
8.9 KiB
YAML
# RUN: llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z16 -verify-machineinstrs \
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# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler 2>&1\
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# RUN: | FileCheck %s
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# REQUIRES: asserts
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# This function has two long independent chains of instructions that should be interleaved.
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# CHECK: ********** MI Scheduling **********
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# CHECK-NEXT: fun0:%bb.0
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# CHECK: ********** MI Scheduling **********
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# CHECK-NEXT: fun0:%bb.1
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# CHECK: Number of nodes in def-use sequences: 10. Latency scheduling enabled for data sequences.
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# CHECK: *** Final schedule for %bb.1 ***
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# CHECK-NEXT: SU(0): %4:fp64bit = LZDR
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# CHECK-NEXT: SU(5): %9:fp64bit = LZDR
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# CHECK-NEXT: SU(1): %5:fp64bit = nofpexcept WFMADB %0:fp64bit, %1:fp64bit, %4:fp64bit, implicit $fpc
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# CHECK-NEXT: SU(6): %10:fp64bit = nofpexcept WFMADB %2:fp64bit, %3:fp64bit, %9:fp64bit, implicit $fpc
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# CHECK-NEXT: SU(2): %6:fp64bit = nofpexcept WFMADB %0:fp64bit, %1:fp64bit, %5:fp64bit, implicit $fpc
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# CHECK-NEXT: SU(7): %11:fp64bit = nofpexcept WFMADB %2:fp64bit, %3:fp64bit, %10:fp64bit, implicit $fpc
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# CHECK-NEXT: SU(3): %7:fp64bit = nofpexcept WFMADB %0:fp64bit, %1:fp64bit, %6:fp64bit, implicit $fpc
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# CHECK-NEXT: SU(8): %12:fp64bit = nofpexcept WFMADB %2:fp64bit, %3:fp64bit, %11:fp64bit, implicit $fpc
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# CHECK-NEXT: SU(4): %8:fp64bit = nofpexcept WFMADB %0:fp64bit, %1:fp64bit, %7:fp64bit, implicit $fpc
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# CHECK-NEXT: SU(9): %13:fp64bit = nofpexcept WFMADB %2:fp64bit, %3:fp64bit, %12:fp64bit, implicit $fpc
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# CHECK-NEXT: SU(10): %14:vr64bit = nofpexcept WFADB %8:fp64bit, %13:fp64bit, implicit $fpc
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# CHECK-NEXT: SU(11): VST64 %14:vr64bit, $noreg, 0, $noreg :: (store (s128) into `ptr null`, align 8)
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---
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name: fun0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f0d, $f2d, $f4d, $f6d
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%0:fp64bit = COPY $f0d
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%1:fp64bit = COPY $f2d
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%2:fp64bit = COPY $f4d
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%3:fp64bit = COPY $f6d
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bb.1:
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%4:fp64bit = LZDR
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%5:fp64bit = nofpexcept WFMADB %0, %1, %4, implicit $fpc
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%6:fp64bit = nofpexcept WFMADB %0, %1, %5, implicit $fpc
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%7:fp64bit = nofpexcept WFMADB %0, %1, %6, implicit $fpc
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%8:fp64bit = nofpexcept WFMADB %0, %1, %7, implicit $fpc
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%9:fp64bit = LZDR
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%10:fp64bit = nofpexcept WFMADB %2, %3, %9, implicit $fpc
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%11:fp64bit = nofpexcept WFMADB %2, %3, %10, implicit $fpc
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%12:fp64bit = nofpexcept WFMADB %2, %3, %11, implicit $fpc
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%13:fp64bit = nofpexcept WFMADB %2, %3, %12, implicit $fpc
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%14:vr64bit = nofpexcept WFADB %8, %13, implicit $fpc
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VST64 %14, $noreg, 0, $noreg :: (store (s128) into `ptr null`, align 8)
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Return
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...
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# This function has a data flow sequence and latency scheduling puts the WFDDB high.
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# CHECK: ********** MI Scheduling **********
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# CHECK-NEXT: fun1:%bb.0
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# CHECK: Number of nodes in def-use sequences: 4. Latency scheduling enabled for data sequences.
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# CHECK: *** Final schedule for %bb.0 ***
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# CHECK-NEXT: SU(1): undef %1.subreg_h64:vr128bit = WFDDB undef %2:fp64bit, undef %3:fp64bit, implicit $fpc
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# CHECK-NEXT: SU(2): %4:fp64bit = COPY %1.subreg_h64:vr128bit
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# CHECK-NEXT: SU(3): %5:fp64bit = WFADB %4:fp64bit, %4:fp64bit, implicit $fpc
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# CHECK-NEXT: SU(0): dead %0:fp64bit = LZDR
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# CHECK-NEXT: SU(4): VST64 %5:fp64bit, $noreg, 0, $noreg :: (store (s128) into `ptr null`, align 8)
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---
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name: fun1
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:fp64bit = LZDR
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undef %1.subreg_h64:vr128bit = WFDDB undef %2:fp64bit, undef %3:fp64bit, implicit $fpc
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%4:fp64bit = COPY %1.subreg_h64:vr128bit
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%5:fp64bit = WFADB %4, %4, implicit $fpc
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VST64 %5:fp64bit , $noreg, 0, $noreg :: (store (s128) into `ptr null`, align 8)
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Return
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...
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# Same, but there is no sequence, so no latency scheduling is done.
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# CHECK: ********** MI Scheduling **********
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# CHECK-NEXT: fun2:%bb.0
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# CHECK: Latency scheduling not enabled for data sequences.
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# CHECK: *** Final schedule for %bb.0 ***
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# CHECK-NEXT: SU(0): dead %0:fp64bit = LZDR
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# CHECK-NEXT: SU(1): undef %1.subreg_h64:vr128bit = WFDDB undef %2:fp64bit, undef %3:fp64bit, implicit $fpc
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# CHECK-NEXT: SU(2): VST64 %1.subreg_h64:vr128bit, $noreg, 0, $noreg :: (store (s128) into `ptr null`, align 8)
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---
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name: fun2
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:fp64bit = LZDR
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undef %1.subreg_h64:vr128bit = WFDDB undef %2:fp64bit, undef %3:fp64bit, implicit $fpc
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VST64 %1.subreg_h64:vr128bit , $noreg, 0, $noreg :: (store (s128) into `ptr null`, align 8)
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Return
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...
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# Use the GenericScheduler latency heuristic for this single block loop.
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# CHECK: ********** MI Scheduling **********
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# CHECK-NEXT: fun3:%bb.1
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# CHECK: Latency scheduling not enabled for data sequences.
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# CHECK: ACYCLIC LATENCY LIMIT
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# CHECK: Pick Bot BOT-HEIGHT [pre-RA]
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---
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name: fun3
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tracksRegLiveness: true
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body: |
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bb.0:
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%19:vr128bit = VREPIF 1
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bb.1:
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%3:gr64bit = VLGVF %19, $noreg, 0
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%6:gr64bit = LLGFR %3.subreg_l32
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%6:gr64bit = MSGFI %6, 274877907
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%7:gr64bit = SRLG %6, $noreg, 39
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%9:gr64bit = VLGVF %19, $noreg, 1
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%12:gr64bit = LLGFR %9.subreg_l32
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%12:gr64bit = MSGFI %12, 274877907
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%13:gr64bit = SRLG %12, $noreg, 39
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%15:vr128bit = VLVGP %13, %13
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%15:vr128bit = VLVGF %15, %7.subreg_l32, $noreg, 0
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%16:vr128bit = VUPLHF %15
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%17:vr128bit = nofpexcept VCDLGB %16, 0, 0, implicit $fpc
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%19:vr128bit = VGBM 0
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%18:vr128bit = nofpexcept VFMDB %17, %19, implicit $fpc
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VST %18, $noreg, 0, $noreg :: (store (s128) into `ptr null`, align 8)
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J %bb.1
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...
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# This region has many nodes compared to the maximum height - the DAG is
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# "wide". Don't interleave the data flows in cases like this, as it could
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# result in too much ILP and spilling.
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# CHECK: ********** MI Scheduling **********
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# CHECK-NEXT: fun4:%bb.0
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# CHECK: Latency scheduling not enabled for data sequences.
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# CHECK: *** Final schedule for %bb.0 ***
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# CHECK-NEXT: SU(0): %0:gr64bit = COPY undef %1:gr64bit
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# CHECK-NEXT: SU(1): dead %2:gr64bit = AGRK %0:gr64bit, %0:gr64bit,
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# CHECK-NEXT: SU(2): %3:gr64bit = COPY undef %1:gr64bit
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# CHECK-NEXT: SU(3): dead %4:gr64bit = AGRK %3:gr64bit, %3:gr64bit,
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# CHECK-NEXT: SU(4): %5:gr64bit = COPY undef %1:gr64bit
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# CHECK-NEXT: SU(5): dead %6:gr64bit = AGRK %5:gr64bit, %5:gr64bit,
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# CHECK-NEXT: SU(6): %7:gr64bit = COPY undef %1:gr64bit
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# CHECK-NEXT: SU(7): dead %8:gr64bit = AGRK %7:gr64bit, %7:gr64bit,
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# CHECK-NEXT: SU(8): %9:gr64bit = COPY undef %1:gr64bit
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# CHECK-NEXT: SU(9): dead %10:gr64bit = AGRK %9:gr64bit, %9:gr64bit,
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# CHECK-NEXT: SU(10): %11:gr64bit = COPY undef %1:gr64bit
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# CHECK-NEXT: SU(11): dead %12:gr64bit = AGRK %11:gr64bit, %11:gr64bit,
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---
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name: fun4
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tracksRegLiveness: true
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body: |
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bb.0:
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%1:gr64bit = COPY undef %0:gr64bit
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%2:gr64bit = AGRK %1, %1, implicit-def dead $cc
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%3:gr64bit = COPY undef %0:gr64bit
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%4:gr64bit = AGRK %3, %3, implicit-def dead $cc
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%5:gr64bit = COPY undef %0:gr64bit
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%6:gr64bit = AGRK %5, %5, implicit-def dead $cc
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%7:gr64bit = COPY undef %0:gr64bit
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%8:gr64bit = AGRK %7, %7, implicit-def dead $cc
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%9:gr64bit = COPY undef %0:gr64bit
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%10:gr64bit = AGRK %9, %9, implicit-def dead $cc
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%11:gr64bit = COPY undef %0:gr64bit
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%12:gr64bit = AGRK %11, %11, implicit-def dead $cc
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Return
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...
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# The TMLL64 should be scheduled first even though the LA is available and of
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# lesser height, because the TMLL64 Depth equals the remaining latency (on CP).
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# CHECK: ********** MI Scheduling **********
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# CHECK-NEXT: fun5:%bb.0
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# CHECK: ********** MI Scheduling **********
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# CHECK-NEXT: fun5:%bb.1
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# CHECK: Number of nodes in def-use sequences: 4. Latency scheduling enabled for data sequences.
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# CHECK: SU(0): dead %2:addr64bit = LA %0:addr64bit, 1, $noreg
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# CHECK-NEXT: # preds left : 0
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# CHECK-NEXT: # succs left : 0
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 1
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# CHECK-NEXT: Depth : 0
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# CHECK-NEXT: Height : 0
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# CHECK: SU(4): TMLL64 %5:gr64bit, 1, implicit-def $cc
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# CHECK-NEXT: # preds left : 1
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# CHECK-NEXT: # succs left : 1
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# CHECK-NEXT: # rdefs left : 0
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# CHECK-NEXT: Latency : 1
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# CHECK-NEXT: Depth : 3
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# CHECK-NEXT: Height : 1
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# CHECK: Queue BotQ.A: 0 4
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# CHECK: *** Final schedule for %bb.1 ***
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# CHECK-NEXT: SU(1): %3:gr64bit = COPY %1:gr32bit
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# CHECK-NEXT: SU(2): %4:gr64bit = COPY %3:gr64bit
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# CHECK-NEXT: SU(3): %5:gr64bit = COPY %4:gr64bit
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# CHECK-NEXT: SU(0): dead %2:addr64bit = LA %0:addr64bit, 1, $noreg
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# CHECK-NEXT: SU(4): TMLL64 %5:gr64bit, 1, implicit-def $cc
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---
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name: fun5
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r2d, $r3l
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%0:addr64bit = COPY $r2d
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%1:gr32bit = COPY $r3l
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bb.1:
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%2:addr64bit = LA %0, 1, $noreg
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%3:gr64bit = COPY %1
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%4:gr64bit = COPY %3
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%5:gr64bit = COPY %4
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TMLL64 %5, 1, implicit-def $cc
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BRC 15, 7, %bb.1, implicit killed $cc
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Return
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...
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