derek.holloway
7502bf64a4
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344 lines
11 KiB
LLVM
344 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <8 x i8> @u_v8i8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: u_v8i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u8 q1, q1
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; CHECK-NEXT: vmovlb.u8 q0, q0
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vmov.i16 q3, #0x1
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; CHECK-NEXT: vcmp.u16 hi, q0, q1
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; CHECK-NEXT: vpsel q2, q3, q2
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; CHECK-NEXT: vmov.i8 q3, #0xff
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; CHECK-NEXT: vcmp.u16 hi, q1, q0
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; CHECK-NEXT: vpsel q0, q3, q2
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; CHECK-NEXT: bx lr
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entry:
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%c = call <8 x i8> @llvm.ucmp(<8 x i8> %a, <8 x i8> %b)
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ret <8 x i8> %c
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}
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define arm_aapcs_vfpcc <16 x i8> @u_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: u_v16i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vmov.i8 q3, #0x1
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; CHECK-NEXT: vcmp.u8 hi, q0, q1
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; CHECK-NEXT: vpsel q2, q3, q2
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; CHECK-NEXT: vmov.i8 q3, #0xff
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; CHECK-NEXT: vcmp.u8 hi, q1, q0
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; CHECK-NEXT: vpsel q0, q3, q2
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; CHECK-NEXT: bx lr
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entry:
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%c = call <16 x i8> @llvm.ucmp(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %c
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}
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define arm_aapcs_vfpcc <4 x i16> @u_v4i16(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: u_v4i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u16 q1, q1
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; CHECK-NEXT: vmovlb.u16 q0, q0
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vmov.i32 q3, #0x1
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; CHECK-NEXT: vcmp.u32 hi, q0, q1
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; CHECK-NEXT: vpsel q2, q3, q2
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; CHECK-NEXT: vmov.i8 q3, #0xff
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; CHECK-NEXT: vcmp.u32 hi, q1, q0
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; CHECK-NEXT: vpsel q0, q3, q2
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; CHECK-NEXT: bx lr
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entry:
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%c = call <4 x i16> @llvm.ucmp(<4 x i16> %a, <4 x i16> %b)
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ret <4 x i16> %c
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}
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define arm_aapcs_vfpcc <8 x i16> @u_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: u_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vmov.i16 q3, #0x1
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; CHECK-NEXT: vcmp.u16 hi, q0, q1
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; CHECK-NEXT: vpsel q2, q3, q2
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; CHECK-NEXT: vmov.i8 q3, #0xff
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; CHECK-NEXT: vcmp.u16 hi, q1, q0
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; CHECK-NEXT: vpsel q0, q3, q2
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; CHECK-NEXT: bx lr
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entry:
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%c = call <8 x i16> @llvm.ucmp(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %c
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}
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define arm_aapcs_vfpcc <16 x i16> @u_v16i16(<16 x i16> %a, <16 x i16> %b) {
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; CHECK-LABEL: u_v16i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: vmov.i32 q4, #0x0
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; CHECK-NEXT: vmov.i16 q5, #0x1
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; CHECK-NEXT: vcmp.u16 hi, q0, q2
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; CHECK-NEXT: vmov.i8 q7, #0xff
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; CHECK-NEXT: vpsel q6, q5, q4
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; CHECK-NEXT: vcmp.u16 hi, q2, q0
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; CHECK-NEXT: vpsel q0, q7, q6
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; CHECK-NEXT: vcmp.u16 hi, q1, q3
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; CHECK-NEXT: vpsel q2, q5, q4
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; CHECK-NEXT: vcmp.u16 hi, q3, q1
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; CHECK-NEXT: vpsel q1, q7, q2
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: bx lr
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entry:
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%c = call <16 x i16> @llvm.ucmp(<16 x i16> %a, <16 x i16> %b)
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ret <16 x i16> %c
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}
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define arm_aapcs_vfpcc <2 x i32> @u_v2i32(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: u_v2i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: vmov.i64 q2, #0xffffffff
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; CHECK-NEXT: movs r4, #0
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; CHECK-NEXT: vand q1, q1, q2
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; CHECK-NEXT: vand q0, q0, q2
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; CHECK-NEXT: vmov lr, r12, d0
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: vmov r3, r8, d2
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; CHECK-NEXT: vmov r6, r7, d3
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: subs.w r1, r3, lr
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; CHECK-NEXT: sbcs.w r1, r8, r12
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; CHECK-NEXT: csetm r1, lo
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; CHECK-NEXT: bfi r4, r1, #0, #8
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; CHECK-NEXT: vmov r1, r5, d1
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; CHECK-NEXT: subs r2, r6, r1
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; CHECK-NEXT: sbcs.w r2, r7, r5
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; CHECK-NEXT: csetm r2, lo
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; CHECK-NEXT: bfi r4, r2, #8, #8
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; CHECK-NEXT: adr r2, .LCPI5_0
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; CHECK-NEXT: vldrw.u32 q0, [r2]
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; CHECK-NEXT: subs.w r2, lr, r3
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; CHECK-NEXT: sbcs.w r2, r12, r8
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; CHECK-NEXT: vmsr p0, r4
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; CHECK-NEXT: csetm r2, lo
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; CHECK-NEXT: subs r1, r1, r6
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; CHECK-NEXT: sbcs.w r1, r5, r7
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; CHECK-NEXT: bfi r0, r2, #0, #8
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; CHECK-NEXT: csetm r1, lo
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bfi r0, r1, #8, #8
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; CHECK-NEXT: vmov.i8 q1, #0xff
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI5_0:
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 0 @ 0x0
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entry:
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%c = call <2 x i32> @llvm.ucmp(<2 x i32> %a, <2 x i32> %b)
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ret <2 x i32> %c
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}
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define arm_aapcs_vfpcc <4 x i32> @u_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: u_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vmov.i32 q3, #0x1
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; CHECK-NEXT: vcmp.u32 hi, q0, q1
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; CHECK-NEXT: vpsel q2, q3, q2
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; CHECK-NEXT: vmov.i8 q3, #0xff
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; CHECK-NEXT: vcmp.u32 hi, q1, q0
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; CHECK-NEXT: vpsel q0, q3, q2
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; CHECK-NEXT: bx lr
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entry:
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%c = call <4 x i32> @llvm.ucmp(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %c
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}
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define arm_aapcs_vfpcc <8 x i32> @u_v8i32(<8 x i32> %a, <8 x i32> %b) {
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; CHECK-LABEL: u_v8i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: vmov.i32 q4, #0x0
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; CHECK-NEXT: vmov.i32 q5, #0x1
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; CHECK-NEXT: vcmp.u32 hi, q0, q2
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; CHECK-NEXT: vmov.i8 q7, #0xff
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; CHECK-NEXT: vpsel q6, q5, q4
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; CHECK-NEXT: vcmp.u32 hi, q2, q0
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; CHECK-NEXT: vpsel q0, q7, q6
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; CHECK-NEXT: vcmp.u32 hi, q1, q3
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; CHECK-NEXT: vpsel q2, q5, q4
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; CHECK-NEXT: vcmp.u32 hi, q3, q1
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; CHECK-NEXT: vpsel q1, q7, q2
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: bx lr
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entry:
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%c = call <8 x i32> @llvm.ucmp(<8 x i32> %a, <8 x i32> %b)
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ret <8 x i32> %c
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}
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define arm_aapcs_vfpcc <2 x i64> @u_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: u_v2i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: vmov lr, r12, d0
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; CHECK-NEXT: movs r4, #0
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; CHECK-NEXT: vmov r3, r8, d2
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: vmov r6, r7, d3
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; CHECK-NEXT: vmov.i32 q1, #0x0
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; CHECK-NEXT: subs.w r1, r3, lr
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; CHECK-NEXT: sbcs.w r1, r8, r12
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; CHECK-NEXT: csetm r1, lo
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; CHECK-NEXT: bfi r4, r1, #0, #8
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; CHECK-NEXT: vmov r1, r5, d1
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; CHECK-NEXT: subs r2, r6, r1
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; CHECK-NEXT: sbcs.w r2, r7, r5
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; CHECK-NEXT: csetm r2, lo
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; CHECK-NEXT: bfi r4, r2, #8, #8
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; CHECK-NEXT: adr r2, .LCPI8_0
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; CHECK-NEXT: vldrw.u32 q0, [r2]
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; CHECK-NEXT: subs.w r2, lr, r3
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; CHECK-NEXT: sbcs.w r2, r12, r8
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; CHECK-NEXT: vmsr p0, r4
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; CHECK-NEXT: csetm r2, lo
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; CHECK-NEXT: subs r1, r1, r6
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; CHECK-NEXT: sbcs.w r1, r5, r7
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; CHECK-NEXT: bfi r0, r2, #0, #8
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; CHECK-NEXT: csetm r1, lo
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bfi r0, r1, #8, #8
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; CHECK-NEXT: vmov.i8 q1, #0xff
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI8_0:
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 0 @ 0x0
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entry:
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%c = call <2 x i64> @llvm.ucmp(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %c
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}
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define arm_aapcs_vfpcc <4 x i64> @u_v4i64(<4 x i64> %a, <4 x i64> %b) {
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; CHECK-LABEL: u_v4i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
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; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
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; CHECK-NEXT: .pad #4
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; CHECK-NEXT: sub sp, #4
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; CHECK-NEXT: .vsave {d8, d9, d10, d11}
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; CHECK-NEXT: vpush {d8, d9, d10, d11}
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; CHECK-NEXT: vmov lr, r12, d0
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; CHECK-NEXT: movs r4, #0
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; CHECK-NEXT: vmov r3, r8, d4
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; CHECK-NEXT: vmov.i32 q5, #0x0
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; CHECK-NEXT: vmov r6, r7, d5
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; CHECK-NEXT: mov.w r9, #0
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; CHECK-NEXT: vmov.i8 q2, #0xff
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; CHECK-NEXT: subs.w r1, r3, lr
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; CHECK-NEXT: sbcs.w r1, r8, r12
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; CHECK-NEXT: csetm r1, lo
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; CHECK-NEXT: bfi r4, r1, #0, #8
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; CHECK-NEXT: vmov r1, r5, d1
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; CHECK-NEXT: subs r2, r6, r1
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; CHECK-NEXT: sbcs.w r2, r7, r5
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; CHECK-NEXT: csetm r2, lo
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; CHECK-NEXT: bfi r4, r2, #8, #8
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; CHECK-NEXT: adr r2, .LCPI9_0
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; CHECK-NEXT: vldrw.u32 q4, [r2]
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; CHECK-NEXT: subs.w r2, lr, r3
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; CHECK-NEXT: sbcs.w r2, r12, r8
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; CHECK-NEXT: mov.w r3, #0
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; CHECK-NEXT: csetm r2, lo
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; CHECK-NEXT: subs r1, r1, r6
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; CHECK-NEXT: sbcs.w r1, r5, r7
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; CHECK-NEXT: bfi r3, r2, #0, #8
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; CHECK-NEXT: csetm r1, lo
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; CHECK-NEXT: vmsr p0, r4
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; CHECK-NEXT: bfi r3, r1, #8, #8
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; CHECK-NEXT: vpsel q0, q4, q5
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; CHECK-NEXT: vmsr p0, r3
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; CHECK-NEXT: vmov lr, r12, d2
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; CHECK-NEXT: vmov r3, r7, d6
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; CHECK-NEXT: movs r5, #0
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; CHECK-NEXT: vmov r2, r1, d7
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; CHECK-NEXT: vpsel q0, q2, q0
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; CHECK-NEXT: subs.w r6, r3, lr
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; CHECK-NEXT: sbcs.w r6, r7, r12
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; CHECK-NEXT: csetm r6, lo
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; CHECK-NEXT: bfi r5, r6, #0, #8
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; CHECK-NEXT: vmov r6, r4, d3
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; CHECK-NEXT: subs r0, r2, r6
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; CHECK-NEXT: sbcs.w r0, r1, r4
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; CHECK-NEXT: csetm r0, lo
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; CHECK-NEXT: bfi r5, r0, #8, #8
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; CHECK-NEXT: subs.w r0, lr, r3
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; CHECK-NEXT: sbcs.w r0, r12, r7
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; CHECK-NEXT: vmsr p0, r5
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; CHECK-NEXT: csetm r0, lo
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; CHECK-NEXT: vpsel q1, q4, q5
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; CHECK-NEXT: bfi r9, r0, #0, #8
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; CHECK-NEXT: subs r0, r6, r2
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; CHECK-NEXT: sbcs.w r0, r4, r1
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; CHECK-NEXT: csetm r0, lo
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; CHECK-NEXT: bfi r9, r0, #8, #8
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; CHECK-NEXT: vmsr p0, r9
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; CHECK-NEXT: vpsel q1, q2, q1
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; CHECK-NEXT: vpop {d8, d9, d10, d11}
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; CHECK-NEXT: add sp, #4
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; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI9_0:
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 0 @ 0x0
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entry:
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%c = call <4 x i64> @llvm.ucmp(<4 x i64> %a, <4 x i64> %b)
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ret <4 x i64> %c
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}
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define arm_aapcs_vfpcc <16 x i8> @signOf_neon(<8 x i16> %s0_lo, <8 x i16> %s0_hi, <8 x i16> %s1_lo, <8 x i16> %s1_hi) {
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; CHECK-LABEL: signOf_neon:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, #16
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; CHECK-NEXT: vmov.i32 q4, #0x0
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; CHECK-NEXT: vmov.i16 q5, #0x1
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; CHECK-NEXT: vcmp.u16 hi, q1, q3
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; CHECK-NEXT: vmov.i8 q7, #0xff
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; CHECK-NEXT: vpsel q6, q5, q4
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; CHECK-NEXT: vcmp.u16 hi, q3, q1
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; CHECK-NEXT: vpsel q1, q7, q6
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; CHECK-NEXT: vcmp.u16 hi, q0, q2
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; CHECK-NEXT: vpsel q3, q5, q4
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; CHECK-NEXT: vcmp.u16 hi, q2, q0
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; CHECK-NEXT: mov r0, sp
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; CHECK-NEXT: vpsel q0, q7, q3
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; CHECK-NEXT: vstrb.16 q1, [r0, #8]
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; CHECK-NEXT: vstrb.16 q0, [r0]
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; CHECK-NEXT: vldrw.u32 q0, [r0]
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; CHECK-NEXT: add sp, #16
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: bx lr
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entry:
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%0 = shufflevector <8 x i16> %s0_lo, <8 x i16> %s0_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%1 = shufflevector <8 x i16> %s1_lo, <8 x i16> %s1_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%or.i = tail call <16 x i8> @llvm.ucmp.v16i8.v16i16(<16 x i16> %0, <16 x i16> %1)
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ret <16 x i8> %or.i
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}
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