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215 lines
6.1 KiB
YAML
215 lines
6.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=i386-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,X86
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,X64
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--- |
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define void @test_copy() {
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ret void
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}
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define void @test_copy2() {
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ret void
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}
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define void @test_copy3() {
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ret void
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}
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define void @test_copy4() {
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ret void
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}
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define void @test_copy5() {
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ret void
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}
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define void @test_copy6() {
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ret void
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}
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...
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---
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name: test_copy
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $eax
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; CHECK-LABEL: name: test_copy
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; CHECK: liveins: $eax
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $al
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; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]]
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; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]]
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; CHECK-NEXT: RET 0, implicit $eax
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%0(s8) = COPY $al
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%1(s32) = G_ZEXT %0(s8)
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$eax = COPY %1(s32)
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RET 0, implicit $eax
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...
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---
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name: test_copy2
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $eax
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; CHECK-LABEL: name: test_copy2
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; CHECK: liveins: $eax
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $al
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; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]]
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; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]]
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; CHECK-NEXT: RET 0, implicit $eax
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%0(s8) = COPY $al
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%1(s32) = G_ZEXT %0(s8)
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$eax = COPY %1(s32)
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RET 0, implicit $eax
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...
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---
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name: test_copy3
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $eax
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; X86-LABEL: name: test_copy3
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; X86: liveins: $eax
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; X86-NEXT: {{ $}}
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; X86-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $ax
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; X86-NEXT: [[COPY1:%[0-9]+]]:gr16_abcd = COPY [[COPY]]
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; X86-NEXT: [[COPY2:%[0-9]+]]:gr8_abcd_l = COPY [[COPY1]].sub_8bit
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; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
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; X86-NEXT: $eax = COPY [[MOVZX32rr8_]]
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; X86-NEXT: RET 0, implicit $eax
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;
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; X64-LABEL: name: test_copy3
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; X64: liveins: $eax
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; X64-NEXT: {{ $}}
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; X64-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $ax
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; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
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; X64-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
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; X64-NEXT: $eax = COPY [[MOVZX32rr8_]]
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; X64-NEXT: RET 0, implicit $eax
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%0(s16) = COPY $ax
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%1(s8) = G_TRUNC %0(s16)
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%2(s32) = G_ZEXT %1(s8)
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: test_copy4
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $eax
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; CHECK-LABEL: name: test_copy4
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; CHECK: liveins: $eax
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $eax
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
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; CHECK-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
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; CHECK-NEXT: $eax = COPY [[MOVZX32rr16_]]
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; CHECK-NEXT: RET 0, implicit $eax
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%0(s32) = COPY $eax
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%1(s16) = G_TRUNC %0(s32)
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%2(s32) = G_ZEXT %1(s16)
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: test_copy5
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $eax,$edx
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; X86-LABEL: name: test_copy5
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; X86: liveins: $eax, $edx
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; X86-NEXT: {{ $}}
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; X86-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
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; X86-NEXT: [[COPY1:%[0-9]+]]:gr32_abcd = COPY [[COPY]]
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; X86-NEXT: [[COPY2:%[0-9]+]]:gr8_abcd_l = COPY [[COPY1]].sub_8bit
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; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
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; X86-NEXT: $eax = COPY [[MOVZX32rr8_]]
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; X86-NEXT: RET 0, implicit $eax
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;
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; X64-LABEL: name: test_copy5
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; X64: liveins: $eax, $edx
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; X64-NEXT: {{ $}}
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; X64-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
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; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
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; X64-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
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; X64-NEXT: $eax = COPY [[MOVZX32rr8_]]
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; X64-NEXT: RET 0, implicit $eax
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%0(s32) = COPY $edx
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%1(s8) = G_TRUNC %0(s32)
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%2(s32) = G_ANYEXT %1(s8)
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: test_copy6
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $eax,$edx
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; CHECK-LABEL: name: test_copy6
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; CHECK: liveins: $eax, $edx
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
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; CHECK-NEXT: [[DEF:%[0-9]+]]:low32_addr_access_rbp = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:low32_addr_access_rbp = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_16bit
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; CHECK-NEXT: $eax = COPY [[INSERT_SUBREG]]
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; CHECK-NEXT: RET 0, implicit $eax
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%0(s32) = COPY $edx
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%1(s16) = G_TRUNC %0(s32)
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%2(s32) = G_ANYEXT %1(s16)
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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