derek.holloway
7502bf64a4
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227 lines
8.0 KiB
LLVM
227 lines
8.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,VTEST,VTEST-AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,VTEST,VTEST-AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+prefer-movmsk-over-vtest | FileCheck %s --check-prefixes=CHECK,MOVMSK,MOVMSK-AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+prefer-movmsk-over-vtest | FileCheck %s --check-prefixes=CHECK,MOVMSK,MOVMSK-AVX2
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declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>)
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declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>)
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; Use widest possible vector for movmsk comparisons (PR37087)
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define i1 @movmskps_noneof_bitcast_v4f64(<4 x double> %a0) {
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; VTEST-LABEL: movmskps_noneof_bitcast_v4f64:
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; VTEST: # %bb.0:
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; VTEST-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; VTEST-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
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; VTEST-NEXT: vtestpd %ymm0, %ymm0
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; VTEST-NEXT: sete %al
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; VTEST-NEXT: vzeroupper
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; VTEST-NEXT: retq
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;
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; MOVMSK-LABEL: movmskps_noneof_bitcast_v4f64:
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; MOVMSK: # %bb.0:
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; MOVMSK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; MOVMSK-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
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; MOVMSK-NEXT: vmovmskpd %ymm0, %eax
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; MOVMSK-NEXT: testl %eax, %eax
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; MOVMSK-NEXT: sete %al
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; MOVMSK-NEXT: vzeroupper
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; MOVMSK-NEXT: retq
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%1 = fcmp oeq <4 x double> %a0, zeroinitializer
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%2 = sext <4 x i1> %1 to <4 x i64>
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%3 = bitcast <4 x i64> %2 to <8 x float>
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%4 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %3)
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%5 = icmp eq i32 %4, 0
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ret i1 %5
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}
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define i1 @movmskps_allof_bitcast_v4f64(<4 x double> %a0) {
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; VTEST-AVX1-LABEL: movmskps_allof_bitcast_v4f64:
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; VTEST-AVX1: # %bb.0:
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; VTEST-AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; VTEST-AVX1-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
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; VTEST-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
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; VTEST-AVX1-NEXT: vtestpd %ymm1, %ymm0
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; VTEST-AVX1-NEXT: setb %al
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; VTEST-AVX1-NEXT: vzeroupper
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; VTEST-AVX1-NEXT: retq
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;
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; VTEST-AVX2-LABEL: movmskps_allof_bitcast_v4f64:
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; VTEST-AVX2: # %bb.0:
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; VTEST-AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; VTEST-AVX2-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
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; VTEST-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
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; VTEST-AVX2-NEXT: vtestpd %ymm1, %ymm0
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; VTEST-AVX2-NEXT: setb %al
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; VTEST-AVX2-NEXT: vzeroupper
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; VTEST-AVX2-NEXT: retq
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;
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; MOVMSK-LABEL: movmskps_allof_bitcast_v4f64:
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; MOVMSK: # %bb.0:
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; MOVMSK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; MOVMSK-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
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; MOVMSK-NEXT: vmovmskpd %ymm0, %eax
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; MOVMSK-NEXT: cmpl $15, %eax
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; MOVMSK-NEXT: sete %al
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; MOVMSK-NEXT: vzeroupper
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; MOVMSK-NEXT: retq
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%1 = fcmp oeq <4 x double> %a0, zeroinitializer
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%2 = sext <4 x i1> %1 to <4 x i64>
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%3 = bitcast <4 x i64> %2 to <8 x float>
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%4 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %3)
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%5 = icmp eq i32 %4, 255
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ret i1 %5
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}
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;
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; Avoid sign extension ops when just extracting the sign bits.
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;
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define i32 @movmskpd_cmpgt_v4i64(<4 x i64> %a0) {
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; CHECK-LABEL: movmskpd_cmpgt_v4i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovmskpd %ymm0, %eax
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%1 = icmp sgt <4 x i64> zeroinitializer, %a0
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%2 = sext <4 x i1> %1 to <4 x i64>
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%3 = bitcast <4 x i64> %2 to <4 x double>
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%4 = tail call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %3)
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ret i32 %4
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}
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define i32 @movmskps_ashr_v8i32(<8 x i32> %a0) {
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; CHECK-LABEL: movmskps_ashr_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovmskps %ymm0, %eax
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%1 = ashr <8 x i32> %a0, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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%2 = bitcast <8 x i32> %1 to <8 x float>
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%3 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %2)
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ret i32 %3
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}
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define i32 @movmskps_sext_v4i64(<4 x i32> %a0) {
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; VTEST-AVX1-LABEL: movmskps_sext_v4i64:
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; VTEST-AVX1: # %bb.0:
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; VTEST-AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
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; VTEST-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
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; VTEST-AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
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; VTEST-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; VTEST-AVX1-NEXT: vmovmskpd %ymm0, %eax
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; VTEST-AVX1-NEXT: vzeroupper
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; VTEST-AVX1-NEXT: retq
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;
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; VTEST-AVX2-LABEL: movmskps_sext_v4i64:
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; VTEST-AVX2: # %bb.0:
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; VTEST-AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
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; VTEST-AVX2-NEXT: vmovmskpd %ymm0, %eax
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; VTEST-AVX2-NEXT: vzeroupper
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; VTEST-AVX2-NEXT: retq
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;
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; MOVMSK-AVX1-LABEL: movmskps_sext_v4i64:
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; MOVMSK-AVX1: # %bb.0:
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; MOVMSK-AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
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; MOVMSK-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
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; MOVMSK-AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
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; MOVMSK-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; MOVMSK-AVX1-NEXT: vmovmskpd %ymm0, %eax
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; MOVMSK-AVX1-NEXT: vzeroupper
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; MOVMSK-AVX1-NEXT: retq
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;
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; MOVMSK-AVX2-LABEL: movmskps_sext_v4i64:
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; MOVMSK-AVX2: # %bb.0:
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; MOVMSK-AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
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; MOVMSK-AVX2-NEXT: vmovmskpd %ymm0, %eax
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; MOVMSK-AVX2-NEXT: vzeroupper
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; MOVMSK-AVX2-NEXT: retq
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%1 = sext <4 x i32> %a0 to <4 x i64>
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%2 = bitcast <4 x i64> %1 to <4 x double>
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%3 = tail call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %2)
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ret i32 %3
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}
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define i32 @movmskps_sext_v8i32(<8 x i16> %a0) {
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; VTEST-AVX1-LABEL: movmskps_sext_v8i32:
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; VTEST-AVX1: # %bb.0:
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; VTEST-AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
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; VTEST-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
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; VTEST-AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
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; VTEST-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; VTEST-AVX1-NEXT: vmovmskps %ymm0, %eax
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; VTEST-AVX1-NEXT: vzeroupper
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; VTEST-AVX1-NEXT: retq
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;
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; VTEST-AVX2-LABEL: movmskps_sext_v8i32:
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; VTEST-AVX2: # %bb.0:
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; VTEST-AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
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; VTEST-AVX2-NEXT: vmovmskps %ymm0, %eax
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; VTEST-AVX2-NEXT: vzeroupper
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; VTEST-AVX2-NEXT: retq
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;
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; MOVMSK-AVX1-LABEL: movmskps_sext_v8i32:
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; MOVMSK-AVX1: # %bb.0:
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; MOVMSK-AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
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; MOVMSK-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
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; MOVMSK-AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
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; MOVMSK-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; MOVMSK-AVX1-NEXT: vmovmskps %ymm0, %eax
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; MOVMSK-AVX1-NEXT: vzeroupper
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; MOVMSK-AVX1-NEXT: retq
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;
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; MOVMSK-AVX2-LABEL: movmskps_sext_v8i32:
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; MOVMSK-AVX2: # %bb.0:
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; MOVMSK-AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
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; MOVMSK-AVX2-NEXT: vmovmskps %ymm0, %eax
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; MOVMSK-AVX2-NEXT: vzeroupper
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; MOVMSK-AVX2-NEXT: retq
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%1 = sext <8 x i16> %a0 to <8 x i32>
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%2 = bitcast <8 x i32> %1 to <8 x float>
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%3 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %2)
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ret i32 %3
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}
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define i32 @movmskps_concat_v4f32(<4 x float> %a0, <4 x float> %a1) {
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; VTEST-LABEL: movmskps_concat_v4f32:
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; VTEST: # %bb.0:
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; VTEST-NEXT: vorps %xmm1, %xmm0, %xmm0
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; VTEST-NEXT: xorl %eax, %eax
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; VTEST-NEXT: vtestps %xmm0, %xmm0
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; VTEST-NEXT: setne %al
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; VTEST-NEXT: negl %eax
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; VTEST-NEXT: retq
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;
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; MOVMSK-LABEL: movmskps_concat_v4f32:
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; MOVMSK: # %bb.0:
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; MOVMSK-NEXT: vorps %xmm1, %xmm0, %xmm0
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; MOVMSK-NEXT: vmovmskps %xmm0, %ecx
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; MOVMSK-NEXT: xorl %eax, %eax
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; MOVMSK-NEXT: negl %ecx
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; MOVMSK-NEXT: sbbl %eax, %eax
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; MOVMSK-NEXT: retq
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%1 = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%2 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %1)
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%3 = icmp ne i32 %2, 0
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%4 = sext i1 %3 to i32
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ret i32 %4
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}
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define i32 @movmskps_demanded_concat_v4f32(<4 x float> %a0, <4 x float> %a1) {
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; CHECK-LABEL: movmskps_demanded_concat_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovmskps %xmm0, %ecx
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; CHECK-NEXT: andl $3, %ecx
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: negl %ecx
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; CHECK-NEXT: sbbl %eax, %eax
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; CHECK-NEXT: retq
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%1 = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%2 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %1)
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%3 = and i32 %2, 3
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%4 = icmp ne i32 %3, 0
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%5 = sext i1 %4 to i32
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ret i32 %5
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}
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