derek.holloway
7502bf64a4
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87 lines
4.3 KiB
LLVM
87 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt < %s -S -passes=msan -msan-check-access-address=0 2>&1 | FileCheck %s
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; RUN: opt < %s -S -passes=msan -msan-check-access-address=0 -msan-track-origins=1 2>&1 | FileCheck %s --check-prefixes=ORIGIN
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon-unknown-linux-musl"
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define void @Store(ptr nocapture %p, i32 %x) nounwind sanitize_memory {
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; CHECK-LABEL: define void @Store(
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; CHECK-SAME: ptr captures(none) [[P:%.*]], i32 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_va_arg_overflow_size_tls, align 4
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i32 8), align 8
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i32
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; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 536870912
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; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP3]] to ptr
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; CHECK-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 4
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; CHECK-NEXT: store i32 [[X]], ptr [[P]], align 4
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; CHECK-NEXT: ret void
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;
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; ORIGIN-LABEL: define void @Store(
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; ORIGIN-SAME: ptr captures(none) [[P:%.*]], i32 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
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; ORIGIN-NEXT: [[ENTRY:.*:]]
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; ORIGIN-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_va_arg_overflow_size_tls, align 4
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; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i32 8), align 8
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; ORIGIN-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i32 8), align 4
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; ORIGIN-NEXT: call void @llvm.donothing()
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; ORIGIN-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i32
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; ORIGIN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], 536870912
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; ORIGIN-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr
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; ORIGIN-NEXT: [[TMP6:%.*]] = add i32 [[TMP4]], 1342177280
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; ORIGIN-NEXT: [[TMP7:%.*]] = inttoptr i32 [[TMP6]] to ptr
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; ORIGIN-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4
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; ORIGIN-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0
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; ORIGIN-NEXT: br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1:![0-9]+]]
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; ORIGIN: [[BB8]]:
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; ORIGIN-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4
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; ORIGIN-NEXT: br label %[[BB9]]
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; ORIGIN: [[BB9]]:
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; ORIGIN-NEXT: store i32 [[X]], ptr [[P]], align 4
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; ORIGIN-NEXT: ret void
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;
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entry:
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store i32 %x, ptr %p, align 4
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ret void
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}
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define i32 @Load(ptr nocapture %p) nounwind sanitize_memory {
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; CHECK-LABEL: define i32 @Load(
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; CHECK-SAME: ptr captures(none) [[P:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_va_arg_overflow_size_tls, align 4
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; CHECK-NEXT: call void @llvm.donothing()
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[P]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i32
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; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 536870912
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; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP3]] to ptr
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; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP4]], align 4
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; CHECK-NEXT: store i32 [[_MSLD]], ptr @__msan_retval_tls, align 8
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; CHECK-NEXT: ret i32 [[TMP1]]
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;
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; ORIGIN-LABEL: define i32 @Load(
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; ORIGIN-SAME: ptr captures(none) [[P:%.*]]) #[[ATTR0]] {
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; ORIGIN-NEXT: [[ENTRY:.*:]]
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; ORIGIN-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_va_arg_overflow_size_tls, align 4
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; ORIGIN-NEXT: call void @llvm.donothing()
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; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, ptr [[P]], align 4
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; ORIGIN-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i32
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; ORIGIN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 536870912
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; ORIGIN-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP3]] to ptr
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; ORIGIN-NEXT: [[TMP5:%.*]] = add i32 [[TMP3]], 1342177280
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; ORIGIN-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP5]] to ptr
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; ORIGIN-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP4]], align 4
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; ORIGIN-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
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; ORIGIN-NEXT: store i32 [[_MSLD]], ptr @__msan_retval_tls, align 8
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; ORIGIN-NEXT: store i32 [[TMP7]], ptr @__msan_retval_origin_tls, align 4
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; ORIGIN-NEXT: ret i32 [[TMP1]]
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;
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entry:
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%0 = load i32, ptr %p, align 4
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ret i32 %0
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}
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;.
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; ORIGIN: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}
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;.
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