derek.holloway
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46 lines
2.0 KiB
TableGen
46 lines
2.0 KiB
TableGen
// RUN: llvm-tblgen -gen-register-bank -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def MyTarget : Target;
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def R0 : Register<"r0">;
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def GR : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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def F0 : Register<"f0">;
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def FR : RegisterClass<"MyTarget", [f32], 32, (add F0)>;
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def V0 : Register<"V0">;
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def VR : RegisterClass<"MyTarget", [v4i8, f32], 32, (add V0)>;
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def AllFloatR : RegisterClass<"MyTarget", [f32], 32, (add F0, V0)>;
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def AnyR : RegisterClass<"MyTarget", [i32, f32, v4i8], 32, (add R0, F0, V0)>;
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def GRRegBank : RegisterBank<"GRB", [GR]>;
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def FRRegBank : RegisterBank<"FRB", [FR]>;
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def VRRegBank : RegisterBank<"VRB", [VR]>;
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// CHECK: #ifdef GET_TARGET_REGBANK_CLASS
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// CHECK: const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
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// CHECK: #ifdef GET_TARGET_REGBANK_IMPL
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// CHECK: const RegisterBank &
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// CHECK-NEXT: MyTargetGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
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// CHECK-NEXT: constexpr uint32_t InvalidRegBankID = uint32_t(MyTarget::InvalidRegBankID) & 3;
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// CHECK-NEXT: static const uint32_t RegClass2RegBank[1] = {
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// CHECK-NEXT: (uint32_t(InvalidRegBankID) << 0) |
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// CHECK-NEXT: (uint32_t(InvalidRegBankID) << 2) |
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// CHECK-NEXT: (uint32_t(MyTarget::FRRegBankID) << 4) | // FRRegClassID
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// CHECK-NEXT: (uint32_t(MyTarget::GRRegBankID) << 6) | // GRRegClassID
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// CHECK-NEXT: (uint32_t(MyTarget::VRRegBankID) << 8) // VRRegClassID
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// CHECK-NEXT: };
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// CHECK-NEXT: const unsigned RegClassID = RC.getID();
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// CHECK-NEXT: if (LLVM_LIKELY(RegClassID < 5)) {
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// CHECK-NEXT: unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
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// CHECK-NEXT: if (RegBankID != InvalidRegBankID)
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// CHECK-NEXT: return getRegBank(RegBankID);
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// CHECK-NEXT: }
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// CHECK-NEXT: llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
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// CHECK-NEXT: }
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