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77 lines
2.0 KiB
TableGen
77 lines
2.0 KiB
TableGen
// RUN: llvm-tblgen -gen-register-info -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def TestInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestInstrInfo;
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let RegistersAreIntervals = 1;
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}
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def sub_lo : SubRegIndex<32>;
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def sub_hi : SubRegIndex<32, 32>;
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let Namespace = "Test" in {
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// Simple 32-bit registers (each gets 1 regunit)
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def R0 : Register<"r0">;
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def R1 : Register<"r1">;
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def R2 : Register<"r2">;
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def R3 : Register<"r3">;
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// 64-bit register composed of R0:R1 (gets 2 regunits)
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def R0_R1 : Register<"r0_r1"> {
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let SubRegs = [R0, R1];
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let SubRegIndices = [sub_lo, sub_hi];
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}
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// 64-bit register composed of R2:R3 (gets 2 regunits)
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def R2_R3 : Register<"r2_r3"> {
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let SubRegs = [R2, R3];
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let SubRegIndices = [sub_lo, sub_hi];
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}
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}
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// CHECK: extern const unsigned TestTargetRegUnitIntervals[][2] = {
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// Sentinel
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// CHECK-NEXT: { 0, 0 },
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// Real values
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// CHECK-NEXT: { 0, 1 },
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// CHECK-NEXT: { 1, 2 },
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// CHECK-NEXT: { 2, 3 },
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// CHECK-NEXT: { 3, 4 },
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let Namespace = "Test" in {
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def R4 : Register<"r4">; // Gets unit 4
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def R5 : Register<"r5">; // Gets unit 5
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def R6 : Register<"r6">; // Gets unit 6
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def R7 : Register<"r7">; // Gets unit 7
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// This register skips R5, creating non-contiguous units {4, 6}
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def R4_R6 : Register<"r4_r6"> {
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let SubRegs = [R4, R6];
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let SubRegIndices = [sub_lo, sub_hi];
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}
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// This register skips R6, creating non-contiguous units {5, 7}
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def R5_R7 : Register<"r4_r6"> {
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let SubRegs = [R5, R7];
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let SubRegIndices = [sub_lo, sub_hi];
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}
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}
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def GPR32 : RegisterClass<"Test", [i32], 32, (add R0, R1, R2, R3)>;
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def GPR64 : RegisterClass<"Test", [i64], 64, (add R0_R1, R2_R3)>;
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// Note R5 is assigned 6,7 so that R6 gets 5,6
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// CHECK-NEXT: { 4, 5 },
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// CHECK-NEXT: { 6, 7 },
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// CHECK-NEXT: { 5, 6 },
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// CHECK-NEXT: { 7, 8 },
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// All contiguous
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// CHECK-NEXT: { 0, 2 },
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// CHECK-NEXT: { 2, 4 },
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// CHECK-NEXT: { 4, 6 },
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// CHECK-NEXT: { 6, 8 },
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// CHECK-NEXT: };
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