derek.holloway
7502bf64a4
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149 lines
8.2 KiB
MLIR
149 lines
8.2 KiB
MLIR
// RUN: mlir-opt -split-input-file -convert-memref-to-spirv %s -o - | FileCheck %s
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module attributes {spirv.target_env = #spirv.target_env<#spirv.vce<v1.3, [Shader], []>, #spirv.resource_limits<>>} {
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// CHECK: func.func @atomic_addi_storage_buffer
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// CHECK-SAME: (%[[VAL:.+]]: i32,
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func.func @atomic_addi_storage_buffer(%value: i32, %memref: memref<2x3x4xi32, #spirv.storage_class<StorageBuffer>>, %i0: index, %i1: index, %i2: index) -> i32 {
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// CHECK: %[[AC:.+]] = spirv.AccessChain
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// CHECK: %[[ATOMIC:.+]] = spirv.AtomicIAdd <Device> <AcquireRelease|UniformMemory> %[[AC]], %[[VAL]] : !spirv.ptr<i32, StorageBuffer>
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// CHECK: return %[[ATOMIC]]
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%0 = memref.atomic_rmw "addi" %value, %memref[%i0, %i1, %i2] : (i32, memref<2x3x4xi32, #spirv.storage_class<StorageBuffer>>) -> i32
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return %0: i32
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}
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// CHECK: func.func @atomic_maxs_workgroup
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// CHECK-SAME: (%[[VAL:.+]]: i32,
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func.func @atomic_maxs_workgroup(%value: i32, %memref: memref<2x3x4xi32, #spirv.storage_class<Workgroup>>, %i0: index, %i1: index, %i2: index) -> i32 {
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// CHECK: %[[AC:.+]] = spirv.AccessChain
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// CHECK: %[[ATOMIC:.+]] = spirv.AtomicSMax <Workgroup> <AcquireRelease|WorkgroupMemory> %[[AC]], %[[VAL]] : !spirv.ptr<i32, Workgroup>
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// CHECK: return %[[ATOMIC]]
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%0 = memref.atomic_rmw "maxs" %value, %memref[%i0, %i1, %i2] : (i32, memref<2x3x4xi32, #spirv.storage_class<Workgroup>>) -> i32
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return %0: i32
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}
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// CHECK: func.func @atomic_maxu_storage_buffer
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// CHECK-SAME: (%[[VAL:.+]]: i32,
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func.func @atomic_maxu_storage_buffer(%value: i32, %memref: memref<2x3x4xi32, #spirv.storage_class<StorageBuffer>>, %i0: index, %i1: index, %i2: index) -> i32 {
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// CHECK: %[[AC:.+]] = spirv.AccessChain
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// CHECK: %[[ATOMIC:.+]] = spirv.AtomicUMax <Device> <AcquireRelease|UniformMemory> %[[AC]], %[[VAL]] : !spirv.ptr<i32, StorageBuffer>
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// CHECK: return %[[ATOMIC]]
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%0 = memref.atomic_rmw "maxu" %value, %memref[%i0, %i1, %i2] : (i32, memref<2x3x4xi32, #spirv.storage_class<StorageBuffer>>) -> i32
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return %0: i32
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}
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// CHECK: func.func @atomic_mins_workgroup
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// CHECK-SAME: (%[[VAL:.+]]: i32,
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func.func @atomic_mins_workgroup(%value: i32, %memref: memref<2x3x4xi32, #spirv.storage_class<Workgroup>>, %i0: index, %i1: index, %i2: index) -> i32 {
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// CHECK: %[[AC:.+]] = spirv.AccessChain
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// CHECK: %[[ATOMIC:.+]] = spirv.AtomicSMin <Workgroup> <AcquireRelease|WorkgroupMemory> %[[AC]], %[[VAL]] : !spirv.ptr<i32, Workgroup>
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// CHECK: return %[[ATOMIC]]
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%0 = memref.atomic_rmw "mins" %value, %memref[%i0, %i1, %i2] : (i32, memref<2x3x4xi32, #spirv.storage_class<Workgroup>>) -> i32
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return %0: i32
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}
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// CHECK: func.func @atomic_minu_storage_buffer
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// CHECK-SAME: (%[[VAL:.+]]: i32,
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func.func @atomic_minu_storage_buffer(%value: i32, %memref: memref<2x3x4xi32, #spirv.storage_class<StorageBuffer>>, %i0: index, %i1: index, %i2: index) -> i32 {
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// CHECK: %[[AC:.+]] = spirv.AccessChain
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// CHECK: %[[ATOMIC:.+]] = spirv.AtomicUMin <Device> <AcquireRelease|UniformMemory> %[[AC]], %[[VAL]] : !spirv.ptr<i32, StorageBuffer>
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// CHECK: return %[[ATOMIC]]
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%0 = memref.atomic_rmw "minu" %value, %memref[%i0, %i1, %i2] : (i32, memref<2x3x4xi32, #spirv.storage_class<StorageBuffer>>) -> i32
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return %0: i32
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}
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// CHECK: func.func @atomic_ori_workgroup
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// CHECK-SAME: (%[[VAL:.+]]: i32,
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func.func @atomic_ori_workgroup(%value: i32, %memref: memref<2x3x4xi32, #spirv.storage_class<Workgroup>>, %i0: index, %i1: index, %i2: index) -> i32 {
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// CHECK: %[[AC:.+]] = spirv.AccessChain
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// CHECK: %[[ATOMIC:.+]] = spirv.AtomicOr <Workgroup> <AcquireRelease|WorkgroupMemory> %[[AC]], %[[VAL]] : !spirv.ptr<i32, Workgroup>
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// CHECK: return %[[ATOMIC]]
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%0 = memref.atomic_rmw "ori" %value, %memref[%i0, %i1, %i2] : (i32, memref<2x3x4xi32, #spirv.storage_class<Workgroup>>) -> i32
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return %0: i32
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}
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// CHECK: func.func @atomic_andi_storage_buffer
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// CHECK-SAME: (%[[VAL:.+]]: i32,
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func.func @atomic_andi_storage_buffer(%value: i32, %memref: memref<2x3x4xi32, #spirv.storage_class<StorageBuffer>>, %i0: index, %i1: index, %i2: index) -> i32 {
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// CHECK: %[[AC:.+]] = spirv.AccessChain
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// CHECK: %[[ATOMIC:.+]] = spirv.AtomicAnd <Device> <AcquireRelease|UniformMemory> %[[AC]], %[[VAL]] : !spirv.ptr<i32, StorageBuffer>
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// CHECK: return %[[ATOMIC]]
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%0 = memref.atomic_rmw "andi" %value, %memref[%i0, %i1, %i2] : (i32, memref<2x3x4xi32, #spirv.storage_class<StorageBuffer>>) -> i32
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return %0: i32
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}
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}
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// -----
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// Check sub-element-width atomic ori on i8 memref (stored as i32 in SPIR-V).
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// The byte index must be divided by 4 to get the i32 index, and the value
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// must be shifted to the correct byte position within the i32.
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module attributes {spirv.target_env = #spirv.target_env<#spirv.vce<v1.3, [Shader], []>, #spirv.resource_limits<>>} {
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// CHECK-LABEL: func.func @atomic_ori_i8_storage_buffer
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func.func @atomic_ori_i8_storage_buffer(%value: i8, %memref: memref<16xi8, #spirv.storage_class<StorageBuffer>>, %i0: index) -> i8 {
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// CHECK: %[[IDX:.+]] = builtin.unrealized_conversion_cast %{{.*}} : index to i32
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// CHECK: %[[MEM:.+]] = builtin.unrealized_conversion_cast %{{.*}} : memref{{.*}} to !spirv.ptr
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// CHECK: %[[VAL:.+]] = builtin.unrealized_conversion_cast %{{.*}} : i8 to i32
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// Compute bit offset: (idx % 4) * 8
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// CHECK-DAG: %[[C4:.+]] = spirv.Constant 4 : i32
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// CHECK-DAG: %[[C8:.+]] = spirv.Constant 8 : i32
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// CHECK: %[[MOD:.+]] = spirv.UMod %[[IDX]], %[[C4]]
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// CHECK: %[[OFFSET:.+]] = spirv.IMul %[[MOD]], %[[C8]]
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// Adjust the access chain index: idx / 4
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// CHECK: %[[DIV:.+]] = spirv.SDiv %[[IDX]], %{{.*}}
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// CHECK: %[[AC:.+]] = spirv.AccessChain %[[MEM]][%{{.*}}, %[[DIV]]]
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// Mask and shift the value
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// CHECK: %[[C255:.+]] = spirv.Constant 255 : i32
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// CHECK: %[[MASKED:.+]] = spirv.BitwiseAnd %[[VAL]], %[[C255]]
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// CHECK: %[[SHIFTED:.+]] = spirv.ShiftLeftLogical %[[MASKED]], %[[OFFSET]]
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// Atomic OR
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// CHECK: %[[ATOMIC:.+]] = spirv.AtomicOr <Device> <AcquireRelease|UniformMemory> %[[AC]], %[[SHIFTED]]
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// Extract old value from result
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// CHECK: spirv.ShiftRightLogical %[[ATOMIC]], %[[OFFSET]]
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// CHECK: spirv.BitwiseAnd
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// CHECK: return
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%0 = memref.atomic_rmw "ori" %value, %memref[%i0] : (i8, memref<16xi8, #spirv.storage_class<StorageBuffer>>) -> i8
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return %0: i8
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}
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}
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// -----
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// Check sub-element-width atomic andi on i8 memref.
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module attributes {spirv.target_env = #spirv.target_env<#spirv.vce<v1.3, [Shader], []>, #spirv.resource_limits<>>} {
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// CHECK-LABEL: func.func @atomic_andi_i8_storage_buffer
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func.func @atomic_andi_i8_storage_buffer(%value: i8, %memref: memref<16xi8, #spirv.storage_class<StorageBuffer>>, %i0: index) -> i8 {
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// CHECK: %[[IDX:.+]] = builtin.unrealized_conversion_cast %{{.*}} : index to i32
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// CHECK: %[[MEM:.+]] = builtin.unrealized_conversion_cast %{{.*}} : memref{{.*}} to !spirv.ptr
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// CHECK: %[[VAL:.+]] = builtin.unrealized_conversion_cast %{{.*}} : i8 to i32
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// CHECK-DAG: %[[C4:.+]] = spirv.Constant 4 : i32
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// CHECK-DAG: %[[C8:.+]] = spirv.Constant 8 : i32
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// CHECK: %[[MOD:.+]] = spirv.UMod %[[IDX]], %[[C4]]
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// CHECK: %[[OFFSET:.+]] = spirv.IMul %[[MOD]], %[[C8]]
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// CHECK: %[[DIV:.+]] = spirv.SDiv %[[IDX]], %{{.*}}
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// CHECK: %[[AC:.+]] = spirv.AccessChain %[[MEM]][%{{.*}}, %[[DIV]]]
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// Build the AND mask: (val << offset) | ~(0xFF << offset)
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// CHECK: %[[C255:.+]] = spirv.Constant 255 : i32
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// CHECK: %[[MASKED:.+]] = spirv.BitwiseAnd %[[VAL]], %[[C255]]
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// CHECK: %[[SHIFTED:.+]] = spirv.ShiftLeftLogical %[[MASKED]], %[[OFFSET]]
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// CHECK: %[[ELEM_SHIFTED:.+]] = spirv.ShiftLeftLogical %[[C255]], %[[OFFSET]]
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// CHECK: %[[NOT_ELEM:.+]] = spirv.Not %[[ELEM_SHIFTED]]
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// CHECK: %[[MASK:.+]] = spirv.BitwiseOr %[[SHIFTED]], %[[NOT_ELEM]]
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// Atomic AND
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// CHECK: %[[ATOMIC:.+]] = spirv.AtomicAnd <Device> <AcquireRelease|UniformMemory> %[[AC]], %[[MASK]]
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// Extract old value
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// CHECK: spirv.ShiftRightLogical %[[ATOMIC]], %[[OFFSET]]
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// CHECK: spirv.BitwiseAnd
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// CHECK: return
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%0 = memref.atomic_rmw "andi" %value, %memref[%i0] : (i8, memref<16xi8, #spirv.storage_class<StorageBuffer>>) -> i8
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return %0: i8
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}
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}
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