derek.holloway
7502bf64a4
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372 lines
10 KiB
YAML
372 lines
10 KiB
YAML
# ########################################################################
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# Copyright (C) 2022-2026 Advanced Micro Devices, Inc. All rights Reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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#
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# ########################################################################
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---
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include: rocsparse_common.yaml
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Definitions:
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- &alpha_beta_range_quick
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- { alpha: 1.0, beta: -1.0, alphai: 1.0, betai: -0.5 }
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- &alpha_beta_range_checkin
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- { alpha: 0.0, beta: 1.0, alphai: 1.5, betai: 0.5 }
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- &alpha_beta_range_nightly
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- { alpha: -0.5, beta: 0.5, alphai: 1.0, betai: -0.5 }
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- { alpha: -1.0, beta: -0.5, alphai: 0.0, betai: 0.0 }
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Tests:
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# Quick
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- name: spmv_bsr
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category: quick
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function: spmv_bsr
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indextype: *i32
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precision: *single_double_precisions
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M: [50]
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N: [50]
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block_dim: [2, 4]
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alpha_beta: *alpha_beta_range_quick
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direction: [rocsparse_direction_row]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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- name: spmv_bsr_file
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category: quick
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function: spmv_bsr
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indextype: *i32
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precision: *single_double_precisions
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block_dim: [5, 8]
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alpha_beta: *alpha_beta_range_quick
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direction: [rocsparse_direction_column]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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filename: [mac_econ_fwd500,
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nos2,
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nos4,
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nos6]
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- name: spmv_bsr_file
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category: quick
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function: spmv_bsr
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indextype: *i32
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precision: *single_only_precisions_complex
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M: 1
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N: 1
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block_dim: [3, 5]
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alpha_beta: *alpha_beta_range_quick
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direction: [rocsparse_direction_row]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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filename: [Chevron2,
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qc2534]
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- name: spmv_bsr
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category: quick
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function: spmv_bsr
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indextype: *i32
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precision: *float32_float64_float64_float64
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M: [50]
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N: [50]
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block_dim: [6, 12]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_row]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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- name: spmv_bsr
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category: quick
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function: spmv_bsr
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indextype: *i32
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precision: *int8_int8_int32_int32_axyt_precision
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M: [50]
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N: [50]
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block_dim: [7, 9]
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alpha_beta: *alpha_beta_range_quick
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direction: [rocsparse_direction_row]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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# Pre-checkin
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- name: spmv_bsr_bad_arg
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category: pre_checkin
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function: spmv_bsr_bad_arg
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex_real
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- name: spmv_bsr
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category: pre_checkin
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function: spmv_bsr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex_real
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M: [100]
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N: [100]
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block_dim: [3]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_column]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_random]
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call_stage_analysis: [false]
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- name: spmv_bsr_file
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category: pre_checkin
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function: spmv_bsr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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block_dim: [6]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_row]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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filename: [nos1,
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nos2,
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nos3,
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nos4,
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nos5,
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nos6,
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nos7]
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- name: spmv_bsr_file
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category: pre_checkin
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function: spmv_bsr
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indextype: *i32
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precision: *single_double_precisions
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block_dim: [4]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_row]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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filename: [rma10,
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mc2depi,
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mac_econ_fwd500]
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- name: spmv_bsr_file
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category: pre_checkin
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function: spmv_bsr
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indextype: *i64
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precision: *single_double_precisions
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block_dim: [5]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_row]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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filename: [ASIC_320k,
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bibd_22_8,
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Chebyshev4]
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- name: spmv_bsr_file
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category: pre_checkin
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function: spmv_bsr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex
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block_dim: [2]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_column]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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filename: [mplate,
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Chevron3]
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- name: spmv_bsr_graph_test
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category: pre_checkin
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function: spmv_bsr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex_real
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M: [500]
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N: [842]
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block_dim: [8]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_column]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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graph_test: true
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call_stage_analysis: [false]
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- name: spmv_bsr
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category: pre_checkin
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function: spmv_bsr
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indextype: *i32_i64
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precision: *float32_float64_float64_float64
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M: [200]
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N: [578, 2000]
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block_dim: [16]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_column]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_random]
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- name: spmv_bsr
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category: pre_checkin
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function: spmv_bsr
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indextype: *i32_i64
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precision: *int8_int8_float32_float32_axyt_precision
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M: [200]
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N: [578, 2000]
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block_dim: [16]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_column]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_random]
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- name: spmv_bsr
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category: pre_checkin
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function: spmv_bsr
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indextype: *i32_i64
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precision: *float16_float16_float32_float32_axyt_precision
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M: [2000]
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N: [2000]
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block_dim: [8]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_column]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_random]
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- name: spmv_bsr
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category: pre_checkin
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function: spmv_bsr
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indextype: *i32_i64
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precision: [*float16_float16_float16_float32_axyt_precision, *bfloat16_bfloat16_bfloat16_float32_axyt_precision]
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M: [2000]
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N: [2000]
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block_dim: [4, 8, 16]
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alpha_beta: *alpha_beta_range_checkin
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direction: *all_rocsparse_direction
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baseA: *all_rocsparse_index_base
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matrix: [rocsparse_matrix_random]
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- name: spmv_bsr
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category: pre_checkin
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function: spmv_bsr
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indextype: *i32_i64
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precision: *bfloat16_bfloat16_float32_float32_axyt_precision
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M: [2000]
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N: [2000]
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block_dim: [9]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_column]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_random]
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- name: spmv_bsr_file
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category: pre_checkin
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function: spmv_bsr
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indextype: *i32_i64
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precision: *float32_cmplx32_cmplx32_cmplx32_axyt_precision
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M: [2000]
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N: [2000]
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block_dim: [4]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_row]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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- name: spmv_bsr_file
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category: pre_checkin
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function: spmv_bsr
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indextype: *i32_i64
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precision: *cmplx32_cmplx64_cmplx64_cmplx64
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M: [2000]
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N: [2000]
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block_dim: [4]
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alpha_beta: *alpha_beta_range_checkin
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direction: [rocsparse_direction_row]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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# Nightly
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- name: spmv_bsr
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category: nightly
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function: spmv_bsr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex_real
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M: [39385, 639102]
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N: [29348, 710341]
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block_dim: [4]
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alpha_beta: *alpha_beta_range_nightly
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direction: [rocsparse_direction_row]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_random]
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- name: spmv_bsr_file
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category: nightly
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function: spmv_bsr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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block_dim: [5]
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alpha_beta: *alpha_beta_range_nightly
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direction: [rocsparse_direction_column]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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filename: [bibd_22_8,
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bmwcra_1,
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amazon0312,
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Chebyshev4,
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sme3Dc,
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shipsec1,
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scircuit]
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- name: spmv_bsr_file
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category: nightly
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function: spmv_bsr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex
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block_dim: [7]
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alpha_beta: *alpha_beta_range_nightly
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direction: [rocsparse_direction_row]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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filename: [Chevron4]
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skip_hardware: gfx1151
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- name: spmv_bsr_file
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category: nightly
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function: spmv_bsr
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indextype: *i32_i64
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precision: *float64_cmplx64_cmplx64_cmplx64_axyt_precision
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M: 1
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N: 1
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block_dim: [7]
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alpha_beta: *alpha_beta_range_nightly
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direction: [rocsparse_direction_column]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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filename: [Chevron3,
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bmwcra_1]
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- name: spmv_bsr_file
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category: nightly
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function: spmv_bsr
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indextype: *i32_i64
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precision: *cmplx32_cmplx64_cmplx64_cmplx64
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M: 1
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N: 1
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block_dim: [7]
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alpha_beta: *alpha_beta_range_nightly
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direction: [rocsparse_direction_column]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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filename: [Chevron3,
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bmwcra_1]
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