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92 lines
5.0 KiB
Plaintext
92 lines
5.0 KiB
Plaintext
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --version 5
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// REQUIRES: amdgpu-registered-target
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1250 -fcuda-is-device -emit-llvm -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1251 -fcuda-is-device -emit-llvm -o - %s | FileCheck %s
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#define __device__ __attribute__((device))
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typedef int v2i __attribute__((ext_vector_type(2)));
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typedef int v4i __attribute__((ext_vector_type(4)));
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template<unsigned AO>
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__device__ void template_cooperative_atomic_store_32x4B(int* gaddr, int val) {
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__builtin_amdgcn_cooperative_atomic_store_32x4B(gaddr, val, AO, "agent");
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}
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__device__ void test_amdgcn_cooperative_atomic_store_32x4B(int* gaddr, int val)
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{
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template_cooperative_atomic_store_32x4B<__ATOMIC_SEQ_CST>(gaddr, val);
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}
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template<unsigned AO>
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__device__ int template_cooperative_atomic_load_32x4B(int* gaddr) {
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return __builtin_amdgcn_cooperative_atomic_load_32x4B(gaddr, AO, "");
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}
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__device__ void test_amdgcn_cooperative_atomic_load_32x4B(int* addr, int *out)
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{
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*out = template_cooperative_atomic_load_32x4B<__ATOMIC_SEQ_CST>(addr);
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}
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// CHECK-LABEL: define dso_local void @_Z42test_amdgcn_cooperative_atomic_store_32x4BPii(
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// CHECK-SAME: ptr noundef [[GADDR:%.*]], i32 noundef [[VAL:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[GADDR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[GADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[GADDR_ADDR]] to ptr
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// CHECK-NEXT: [[VAL_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VAL_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[GADDR]], ptr [[GADDR_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR_ASCAST]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GADDR_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[VAL_ADDR_ASCAST]], align 4
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// CHECK-NEXT: call void @_Z39template_cooperative_atomic_store_32x4BILj5EEvPii(ptr noundef [[TMP0]], i32 noundef [[TMP1]]) #[[ATTR3:[0-9]+]]
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// CHECK-NEXT: ret void
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//
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//
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// CHECK-LABEL: define linkonce_odr void @_Z39template_cooperative_atomic_store_32x4BILj5EEvPii(
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// CHECK-SAME: ptr noundef [[GADDR:%.*]], i32 noundef [[VAL:%.*]]) #[[ATTR0]] comdat {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[GADDR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[GADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[GADDR_ADDR]] to ptr
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// CHECK-NEXT: [[VAL_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VAL_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[GADDR]], ptr [[GADDR_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR_ASCAST]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GADDR_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[VAL_ADDR_ASCAST]], align 4
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// CHECK-NEXT: call void @llvm.amdgcn.cooperative.atomic.store.32x4B.p0(ptr [[TMP0]], i32 [[TMP1]], i32 5, metadata [[META4:![0-9]+]])
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// CHECK-NEXT: ret void
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//
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//
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// CHECK-LABEL: define dso_local void @_Z41test_amdgcn_cooperative_atomic_load_32x4BPiS_(
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// CHECK-SAME: ptr noundef [[ADDR:%.*]], ptr noundef [[OUT:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[ADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR_ADDR]] to ptr
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z38template_cooperative_atomic_load_32x4BILj5EEiPi(ptr noundef [[TMP0]]) #[[ATTR3]]
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// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store i32 [[CALL]], ptr [[TMP1]], align 4
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// CHECK-NEXT: ret void
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//
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//
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// CHECK-LABEL: define linkonce_odr noundef i32 @_Z38template_cooperative_atomic_load_32x4BILj5EEiPi(
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// CHECK-SAME: ptr noundef [[GADDR:%.*]]) #[[ATTR0]] comdat {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[GADDR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[GADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[GADDR_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[GADDR]], ptr [[GADDR_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GADDR_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.cooperative.atomic.load.32x4B.p0(ptr [[TMP0]], i32 5, metadata [[META5:![0-9]+]])
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// CHECK-NEXT: ret i32 [[TMP1]]
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//
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//.
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// CHECK: [[META4]] = !{!"agent"}
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// CHECK: [[META5]] = !{!""}
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//.
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