derek.holloway
7502bf64a4
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69 lines
1.9 KiB
LLVM
69 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=mips -mattr=+single-float < %s | FileCheck %s --check-prefix=MIPS32
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; RUN: llc -mtriple=mips64 -mattr=+single-float < %s | FileCheck %s --check-prefix=MIPS64
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define void @read_double(ptr %0) {
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; MIPS32-LABEL: read_double:
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; MIPS32: # %bb.0:
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; MIPS32-NEXT: lw $2, 4($4)
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; MIPS32-NEXT: lw $3, 0($4)
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; MIPS32-NEXT: #APP
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; MIPS32-NEXT: #NO_APP
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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;
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; MIPS64-LABEL: read_double:
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; MIPS64: # %bb.0:
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; MIPS64-NEXT: ld $2, 0($4)
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; MIPS64-NEXT: #APP
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; MIPS64-NEXT: #NO_APP
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: nop
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%2 = load double, ptr %0, align 8
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tail call void asm sideeffect "", "r,~{$1}"(double %2)
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ret void
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}
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define void @read_float(ptr %0) {
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; MIPS32-LABEL: read_float:
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; MIPS32: # %bb.0:
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; MIPS32-NEXT: lwc1 $f0, 0($4)
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; MIPS32-NEXT: #APP
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; MIPS32-NEXT: #NO_APP
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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;
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; MIPS64-LABEL: read_float:
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; MIPS64: # %bb.0:
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; MIPS64-NEXT: lwc1 $f0, 0($4)
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; MIPS64-NEXT: #APP
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; MIPS64-NEXT: #NO_APP
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: nop
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%2 = load float, ptr %0, align 8
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tail call void asm sideeffect "", "f"(float %2)
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ret void
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}
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; Test that a proper register class is assigned to clobbers in single-float mode
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define float @explicit_float_register_clobber(ptr %0) {
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; MIPS32-LABEL: explicit_float_register_clobber:
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; MIPS32: # %bb.0:
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; MIPS32-NEXT: lwc1 $f1, 0($4)
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; MIPS32-NEXT: #APP
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; MIPS32-NEXT: #NO_APP
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: mov.s $f0, $f1
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;
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; MIPS64-LABEL: explicit_float_register_clobber:
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; MIPS64: # %bb.0:
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; MIPS64-NEXT: lwc1 $f1, 0($4)
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; MIPS64-NEXT: #APP
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; MIPS64-NEXT: #NO_APP
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; MIPS64-NEXT: jr $ra
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; MIPS64-NEXT: mov.s $f0, $f1
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%2 = load float, ptr %0, align 8
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tail call void asm sideeffect "", "~{$f0}"()
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ret float %2
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}
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